diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-08-27 11:28:09 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:02 -0400 |
commit | a02eb8da02741f43efb6f06adf534f9f2b913d80 (patch) | |
tree | 3913502d4c3e371a872fdcc1cf1484a8eb366dd4 /arch/mips/tx4927/toshiba_rbtx4927 | |
parent | 4e45171c4e31578157189ca22cfb7b2bcc5f69f2 (diff) |
[MIPS] tx4927: Cleanup unused macros and non-standard IO accessors.
This patch removes many unused constants, replaces non-standard IO
accessors with standard ones, and kills terrible tx4927_mips.h file.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/tx4927/toshiba_rbtx4927')
-rw-r--r-- | arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | 21 | ||||
-rw-r--r-- | arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c | 32 |
2 files changed, 24 insertions, 29 deletions
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c index 551235648811..305eb12f84cc 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c | |||
@@ -204,8 +204,8 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { | |||
204 | .mask_ack = toshiba_rbtx4927_irq_ioc_disable, | 204 | .mask_ack = toshiba_rbtx4927_irq_ioc_disable, |
205 | .unmask = toshiba_rbtx4927_irq_ioc_enable, | 205 | .unmask = toshiba_rbtx4927_irq_ioc_enable, |
206 | }; | 206 | }; |
207 | #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 | 207 | #define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL |
208 | #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 | 208 | #define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL |
209 | 209 | ||
210 | 210 | ||
211 | u32 bit2num(u32 num) | 211 | u32 bit2num(u32 num) |
@@ -224,7 +224,7 @@ int toshiba_rbtx4927_irq_nested(int sw_irq) | |||
224 | { | 224 | { |
225 | u32 level3; | 225 | u32 level3; |
226 | 226 | ||
227 | level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; | 227 | level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; |
228 | if (level3) { | 228 | if (level3) { |
229 | sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); | 229 | sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); |
230 | if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { | 230 | if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { |
@@ -288,9 +288,9 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) | |||
288 | panic("\n"); | 288 | panic("\n"); |
289 | } | 289 | } |
290 | 290 | ||
291 | v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); | 291 | v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); |
292 | v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); | 292 | v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); |
293 | TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); | 293 | writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); |
294 | } | 294 | } |
295 | 295 | ||
296 | 296 | ||
@@ -308,9 +308,10 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) | |||
308 | panic("\n"); | 308 | panic("\n"); |
309 | } | 309 | } |
310 | 310 | ||
311 | v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); | 311 | v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB); |
312 | v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); | 312 | v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); |
313 | TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); | 313 | writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB); |
314 | mmiowb(); | ||
314 | } | 315 | } |
315 | 316 | ||
316 | 317 | ||
@@ -387,12 +388,12 @@ void toshiba_rbtx4927_irq_dump_pics(char *s) | |||
387 | level1_m = level0_m; | 388 | level1_m = level0_m; |
388 | level1_s = level0_s & 0x87; | 389 | level1_s = level0_s & 0x87; |
389 | 390 | ||
390 | level2 = TX4927_RD(0xff1ff6a0); | 391 | level2 = __raw_readl((void __iomem *)0xff1ff6a0UL); |
391 | level2_p = (((level2 & 0x10000)) ? 0 : 1); | 392 | level2_p = (((level2 & 0x10000)) ? 0 : 1); |
392 | level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); | 393 | level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); |
393 | 394 | ||
394 | level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; | 395 | level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; |
395 | level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; | 396 | level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; |
396 | 397 | ||
397 | level4_m = inb(0x21); | 398 | level4_m = inb(0x21); |
398 | outb(0x0A, 0x20); | 399 | outb(0x0A, 0x20); |
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c index 3e84237abe63..4f302062b2d6 100644 --- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c +++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c | |||
@@ -679,25 +679,30 @@ void __init tx4927_pci_setup(void) | |||
679 | 679 | ||
680 | #endif /* CONFIG_PCI */ | 680 | #endif /* CONFIG_PCI */ |
681 | 681 | ||
682 | static void __noreturn wait_forever(void) | ||
683 | { | ||
684 | while (1) | ||
685 | if (cpu_wait) | ||
686 | (*cpu_wait)(); | ||
687 | } | ||
688 | |||
682 | void toshiba_rbtx4927_restart(char *command) | 689 | void toshiba_rbtx4927_restart(char *command) |
683 | { | 690 | { |
684 | printk(KERN_NOTICE "System Rebooting...\n"); | 691 | printk(KERN_NOTICE "System Rebooting...\n"); |
685 | 692 | ||
686 | /* enable the s/w reset register */ | 693 | /* enable the s/w reset register */ |
687 | reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); | 694 | writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE); |
688 | 695 | ||
689 | /* wait for enable to be seen */ | 696 | /* wait for enable to be seen */ |
690 | while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & | 697 | while ((readb(RBTX4927_SW_RESET_ENABLE) & |
691 | RBTX4927_SW_RESET_ENABLE_SET) == 0x00); | 698 | RBTX4927_SW_RESET_ENABLE_SET) == 0x00); |
692 | 699 | ||
693 | /* do a s/w reset */ | 700 | /* do a s/w reset */ |
694 | reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); | 701 | writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO); |
695 | 702 | ||
696 | /* do something passive while waiting for reset */ | 703 | /* do something passive while waiting for reset */ |
697 | local_irq_disable(); | 704 | local_irq_disable(); |
698 | while (1) | 705 | wait_forever(); |
699 | asm_wait(); | ||
700 | |||
701 | /* no return */ | 706 | /* no return */ |
702 | } | 707 | } |
703 | 708 | ||
@@ -706,9 +711,7 @@ void toshiba_rbtx4927_halt(void) | |||
706 | { | 711 | { |
707 | printk(KERN_NOTICE "System Halted\n"); | 712 | printk(KERN_NOTICE "System Halted\n"); |
708 | local_irq_disable(); | 713 | local_irq_disable(); |
709 | while (1) { | 714 | wait_forever(); |
710 | asm_wait(); | ||
711 | } | ||
712 | /* no return */ | 715 | /* no return */ |
713 | } | 716 | } |
714 | 717 | ||
@@ -720,7 +723,7 @@ void toshiba_rbtx4927_power_off(void) | |||
720 | 723 | ||
721 | void __init toshiba_rbtx4927_setup(void) | 724 | void __init toshiba_rbtx4927_setup(void) |
722 | { | 725 | { |
723 | vu32 cp0_config; | 726 | u32 cp0_config; |
724 | char *argptr; | 727 | char *argptr; |
725 | 728 | ||
726 | printk("CPU is %s\n", toshiba_name); | 729 | printk("CPU is %s\n", toshiba_name); |
@@ -747,15 +750,6 @@ void __init toshiba_rbtx4927_setup(void) | |||
747 | } | 750 | } |
748 | #endif | 751 | #endif |
749 | 752 | ||
750 | /* setup serial stuff */ | ||
751 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, | ||
752 | ":Setting up tx4927 sio.\n"); | ||
753 | TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */ | ||
754 | TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */ | ||
755 | |||
756 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, | ||
757 | "+\n"); | ||
758 | |||
759 | set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); | 753 | set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); |
760 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, | 754 | TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, |
761 | ":mips_io_port_base=0x%08lx\n", | 755 | ":mips_io_port_base=0x%08lx\n", |