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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2008-06-27 17:52:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-03 14:14:27 -0400
commit7e3297dc280f88ec0c6619a895f3d449776f952e (patch)
treeb67495185c12a6477de506a44ebaf169de4f1f46 /arch/mips/sni
parent1faf7f25b2aa4fcd2ae0ec2fd2e9fb9ff4bfee10 (diff)
[MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES
The introduction of a real dma cache invalidate makes it important to have a correct cache line size, otherwise the kernel will gives out two memory segment, which might share one cache line. The R4400 Indy/Indigo2 CPU modules are using a second level cache line size of 128 bytes, so MIPS_L1_CACHE_SHIFT needs to be bumped up to 7 for IP22. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sni')
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