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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/sni
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/sni')
-rw-r--r--arch/mips/sni/Makefile7
-rw-r--r--arch/mips/sni/int-handler.S106
-rw-r--r--arch/mips/sni/irq.c194
-rw-r--r--arch/mips/sni/pcimt_scache.c37
-rw-r--r--arch/mips/sni/reset.c51
-rw-r--r--arch/mips/sni/setup.c203
6 files changed, 598 insertions, 0 deletions
diff --git a/arch/mips/sni/Makefile b/arch/mips/sni/Makefile
new file mode 100644
index 000000000000..1e5676e4be86
--- /dev/null
+++ b/arch/mips/sni/Makefile
@@ -0,0 +1,7 @@
1#
2# Makefile for the SNI specific part of the kernel
3#
4
5obj-y += int-handler.o irq.o pcimt_scache.o reset.o setup.o
6
7EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sni/int-handler.S b/arch/mips/sni/int-handler.S
new file mode 100644
index 000000000000..2cdc09f55f18
--- /dev/null
+++ b/arch/mips/sni/int-handler.S
@@ -0,0 +1,106 @@
1/*
2 * SNI RM200 PCI specific interrupt handler code.
3 *
4 * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle
5 */
6#include <asm/asm.h>
7#include <asm/mipsregs.h>
8#include <asm/regdef.h>
9#include <asm/sni.h>
10#include <asm/stackframe.h>
11
12/*
13 * The PCI ASIC has the nasty property that it may delay writes if it is busy.
14 * As a consequence from writes that have not graduated when we exit from the
15 * interrupt handler we might catch a spurious interrupt. To avoid this we
16 * force the PCI ASIC to graduate all writes by executing a read from the
17 * PCI bus.
18 */
19 .set noreorder
20 .set noat
21 .align 5
22 NESTED(sni_rm200_pci_handle_int, PT_SIZE, sp)
23 SAVE_ALL
24 CLI
25 .set at
26
27 /* Blinken light ... */
28 lb t0, led_cache
29 addiu t0, 1
30 sb t0, led_cache
31 sb t0, PCIMT_CSLED # write only register
32 .data
33led_cache: .byte 0
34 .text
35
36 mfc0 t0, CP0_STATUS
37 mfc0 t1, CP0_CAUSE
38 and t0, t1
39
40 andi t1, t0, 0x0800 # hardware interrupt 1
41 bnez t1, _hwint1
42 andi t1, t0, 0x4000 # hardware interrupt 4
43 bnez t1, _hwint4
44 andi t1, t0, 0x2000 # hardware interrupt 3
45 bnez t1, _hwint3
46 andi t1, t0, 0x1000 # hardware interrupt 2
47 bnez t1, _hwint2
48 andi t1, t0, 0x8000 # hardware interrupt 5
49 bnez t1, _hwint5
50 andi t1, t0, 0x0400 # hardware interrupt 0
51 bnez t1, _hwint0
52 nop
53
54 j restore_all # spurious interrupt
55 nop
56
57 ##############################################################################
58
59/* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
60 button interrupts. */
61_hwint0: jal pciasic_hwint0
62 move a0, sp
63 j ret_from_irq
64 nop
65
66/*
67 * hwint 1 deals with EISA and SCSI interrupts
68 */
69_hwint1: jal pciasic_hwint1
70 move a0, sp
71 j ret_from_irq
72 nop
73
74
75/*
76 * This interrupt was used for the com1 console on the first prototypes;
77 * it's unsed otherwise
78 */
79_hwint2: jal pciasic_hwint2
80 move a0, sp
81 j ret_from_irq
82 nop
83
84/*
85 * hwint 3 are the PCI interrupts A - D
86 */
87_hwint3: jal pciasic_hwint3
88 move a0, sp
89 j ret_from_irq
90 nop
91
92/*
93 * hwint 4 is used for only the onboard PCnet 32.
94 */
95_hwint4: jal pciasic_hwint4
96 move a0, sp
97 j ret_from_irq
98 nop
99
100/* hwint5 is the r4k count / compare interrupt */
101_hwint5: jal pciasic_hwint5
102 move a0, sp
103 j ret_from_irq
104 nop
105
106 END(sni_rm200_pci_handle_int)
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
new file mode 100644
index 000000000000..62c760f14674
--- /dev/null
+++ b/arch/mips/sni/irq.c
@@ -0,0 +1,194 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 */
9#include <linux/delay.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15
16#include <asm/i8259.h>
17#include <asm/io.h>
18#include <asm/sni.h>
19
20DEFINE_SPINLOCK(pciasic_lock);
21
22extern asmlinkage void sni_rm200_pci_handle_int(void);
23
24static void enable_pciasic_irq(unsigned int irq)
25{
26 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
27 unsigned long flags;
28
29 spin_lock_irqsave(&pciasic_lock, flags);
30 *(volatile u8 *) PCIMT_IRQSEL |= mask;
31 spin_unlock_irqrestore(&pciasic_lock, flags);
32}
33
34static unsigned int startup_pciasic_irq(unsigned int irq)
35{
36 enable_pciasic_irq(irq);
37 return 0; /* never anything pending */
38}
39
40#define shutdown_pciasic_irq disable_pciasic_irq
41
42void disable_pciasic_irq(unsigned int irq)
43{
44 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
45 unsigned long flags;
46
47 spin_lock_irqsave(&pciasic_lock, flags);
48 *(volatile u8 *) PCIMT_IRQSEL &= mask;
49 spin_unlock_irqrestore(&pciasic_lock, flags);
50}
51
52#define mask_and_ack_pciasic_irq disable_pciasic_irq
53
54static void end_pciasic_irq(unsigned int irq)
55{
56 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
57 enable_pciasic_irq(irq);
58}
59
60static struct hw_interrupt_type pciasic_irq_type = {
61 "ASIC-PCI",
62 startup_pciasic_irq,
63 shutdown_pciasic_irq,
64 enable_pciasic_irq,
65 disable_pciasic_irq,
66 mask_and_ack_pciasic_irq,
67 end_pciasic_irq,
68 NULL
69};
70
71/*
72 * hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
73 * button interrupts. Later ...
74 */
75void pciasic_hwint0(struct pt_regs *regs)
76{
77 panic("Received int0 but no handler yet ...");
78}
79
80/* This interrupt was used for the com1 console on the first prototypes. */
81void pciasic_hwint2(struct pt_regs *regs)
82{
83 /* I think this shouldn't happen on production machines. */
84 panic("hwint2 and no handler yet");
85}
86
87/* hwint5 is the r4k count / compare interrupt */
88void pciasic_hwint5(struct pt_regs *regs)
89{
90 panic("hwint5 and no handler yet");
91}
92
93static unsigned int ls1bit8(unsigned int x)
94{
95 int b = 7, s;
96
97 s = 4; if ((x & 0x0f) == 0) s = 0; b -= s; x <<= s;
98 s = 2; if ((x & 0x30) == 0) s = 0; b -= s; x <<= s;
99 s = 1; if ((x & 0x40) == 0) s = 0; b -= s;
100
101 return b;
102}
103
104/*
105 * hwint 1 deals with EISA and SCSI interrupts,
106 *
107 * The EISA_INT bit in CSITPEND is high active, all others are low active.
108 */
109void pciasic_hwint1(struct pt_regs *regs)
110{
111 u8 pend = *(volatile char *)PCIMT_CSITPEND;
112 unsigned long flags;
113
114 if (pend & IT_EISA) {
115 int irq;
116 /*
117 * Note: ASIC PCI's builtin interrupt achknowledge feature is
118 * broken. Using it may result in loss of some or all i8259
119 * interupts, so don't use PCIMT_INT_ACKNOWLEDGE ...
120 */
121 irq = i8259_irq();
122 if (unlikely(irq < 0))
123 return;
124
125 do_IRQ(irq, regs);
126 }
127
128 if (!(pend & IT_SCSI)) {
129 flags = read_c0_status();
130 clear_c0_status(ST0_IM);
131 do_IRQ(PCIMT_IRQ_SCSI, regs);
132 write_c0_status(flags);
133 }
134}
135
136/*
137 * hwint 3 should deal with the PCI A - D interrupts,
138 */
139void pciasic_hwint3(struct pt_regs *regs)
140{
141 u8 pend = *(volatile char *)PCIMT_CSITPEND;
142 int irq;
143
144 pend &= (IT_INTA | IT_INTB | IT_INTC | IT_INTD);
145 clear_c0_status(IE_IRQ3);
146 irq = PCIMT_IRQ_INT2 + ls1bit8(pend);
147 do_IRQ(irq, regs);
148 set_c0_status(IE_IRQ3);
149}
150
151/*
152 * hwint 4 is used for only the onboard PCnet 32.
153 */
154void pciasic_hwint4(struct pt_regs *regs)
155{
156 clear_c0_status(IE_IRQ4);
157 do_IRQ(PCIMT_IRQ_ETHERNET, regs);
158 set_c0_status(IE_IRQ4);
159}
160
161void __init init_pciasic(void)
162{
163 unsigned long flags;
164
165 spin_lock_irqsave(&pciasic_lock, flags);
166 * (volatile u8 *) PCIMT_IRQSEL =
167 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
168 spin_unlock_irqrestore(&pciasic_lock, flags);
169}
170
171/*
172 * On systems with i8259-style interrupt controllers we assume for
173 * driver compatibility reasons interrupts 0 - 15 to be the i8295
174 * interrupts even if the hardware uses a different interrupt numbering.
175 */
176void __init arch_init_irq(void)
177{
178 int i;
179
180 set_except_vector(0, sni_rm200_pci_handle_int);
181
182 init_i8259_irqs(); /* Integrated i8259 */
183 init_pciasic();
184
185 /* Actually we've got more interrupts to handle ... */
186 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) {
187 irq_desc[i].status = IRQ_DISABLED;
188 irq_desc[i].action = 0;
189 irq_desc[i].depth = 1;
190 irq_desc[i].handler = &pciasic_irq_type;
191 }
192
193 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
194}
diff --git a/arch/mips/sni/pcimt_scache.c b/arch/mips/sni/pcimt_scache.c
new file mode 100644
index 000000000000..a59d457fa8b1
--- /dev/null
+++ b/arch/mips/sni/pcimt_scache.c
@@ -0,0 +1,37 @@
1/*
2 * arch/mips/sni/pcimt_scache.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 1997, 1998 by Ralf Baechle
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <asm/bcache.h>
13#include <asm/sni.h>
14
15#define cacheconf (*(volatile unsigned int *)PCIMT_CACHECONF)
16#define invspace (*(volatile unsigned int *)PCIMT_INVSPACE)
17
18void __init sni_pcimt_sc_init(void)
19{
20 unsigned int scsiz, sc_size;
21
22 scsiz = cacheconf & 7;
23 if (scsiz == 0) {
24 printk("Second level cache is deactived.\n");
25 return;
26 }
27 if (scsiz >= 6) {
28 printk("Invalid second level cache size configured, "
29 "deactivating second level cache.\n");
30 cacheconf = 0;
31 return;
32 }
33
34 sc_size = 128 << scsiz;
35 printk("%dkb second level cache detected, deactivating.\n", sc_size);
36 cacheconf = 0;
37}
diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c
new file mode 100644
index 000000000000..be85bec002e1
--- /dev/null
+++ b/arch/mips/sni/reset.c
@@ -0,0 +1,51 @@
1/*
2 * linux/arch/mips/sni/process.c
3 *
4 * Reset a SNI machine.
5 */
6#include <asm/io.h>
7#include <asm/reboot.h>
8#include <asm/system.h>
9#include <asm/sni.h>
10
11/*
12 * This routine reboots the machine by asking the keyboard
13 * controller to pulse the reset-line low. We try that for a while,
14 * and if it doesn't work, we do some other stupid things.
15 */
16static inline void
17kb_wait(void)
18{
19 int i;
20
21 for (i=0; i<0x10000; i++)
22 if ((inb_p(0x64) & 0x02) == 0)
23 break;
24}
25
26/* XXX This ends up at the ARC firmware prompt ... */
27void sni_machine_restart(char *command)
28{
29 int i, j;
30
31 /* This does a normal via the keyboard controller like a PC.
32 We can do that easier ... */
33 local_irq_disable();
34 for (;;) {
35 for (i=0; i<100; i++) {
36 kb_wait();
37 for(j = 0; j < 100000 ; j++)
38 /* nothing */;
39 outb_p(0xfe,0x64); /* pulse reset low */
40 }
41 }
42}
43
44void sni_machine_halt(void)
45{
46}
47
48void sni_machine_power_off(void)
49{
50 *(volatile unsigned char *)PCIMT_CSWCSM = 0xfd;
51}
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
new file mode 100644
index 000000000000..8f67cee4317b
--- /dev/null
+++ b/arch/mips/sni/setup.c
@@ -0,0 +1,203 @@
1/*
2 * Setup pointers to hardware-dependent routines.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 97, 98, 2000, 03, 04 Ralf Baechle (ralf@linux-mips.org)
9 */
10#include <linux/config.h>
11#include <linux/eisa.h>
12#include <linux/hdreg.h>
13#include <linux/ioport.h>
14#include <linux/sched.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17#include <linux/mc146818rtc.h>
18#include <linux/pci.h>
19#include <linux/console.h>
20#include <linux/fb.h>
21#include <linux/tty.h>
22
23#include <asm/arc/types.h>
24#include <asm/sgialib.h>
25#include <asm/bcache.h>
26#include <asm/bootinfo.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/mc146818-time.h>
30#include <asm/processor.h>
31#include <asm/ptrace.h>
32#include <asm/reboot.h>
33#include <asm/sni.h>
34#include <asm/time.h>
35#include <asm/traps.h>
36
37extern void sni_machine_restart(char *command);
38extern void sni_machine_halt(void);
39extern void sni_machine_power_off(void);
40
41static void __init sni_rm200_pci_timer_setup(struct irqaction *irq)
42{
43 /* set the clock to 100 Hz */
44 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
45 outb_p(LATCH & 0xff , 0x40); /* LSB */
46 outb(LATCH >> 8 , 0x40); /* MSB */
47 setup_irq(0, irq);
48}
49
50/*
51 * A bit more gossip about the iron we're running on ...
52 */
53static inline void sni_pcimt_detect(void)
54{
55 char boardtype[80];
56 unsigned char csmsr;
57 char *p = boardtype;
58 unsigned int asic;
59
60 csmsr = *(volatile unsigned char *)PCIMT_CSMSR;
61
62 p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
63 if ((csmsr & 0x80) == 0)
64 p += sprintf(p, ", board revision %s",
65 (csmsr & 0x20) ? "D" : "C");
66 asic = csmsr & 0x80;
67 asic = (csmsr & 0x08) ? asic : !asic;
68 p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
69 printk("%s.\n", boardtype);
70}
71
72static void __init sni_display_setup(void)
73{
74#ifdef CONFIG_VT
75#if defined(CONFIG_VGA_CONSOLE)
76 struct screen_info *si = &screen_info;
77 DISPLAY_STATUS *di;
78
79 di = ArcGetDisplayStatus(1);
80
81 if (di) {
82 si->orig_x = di->CursorXPosition;
83 si->orig_y = di->CursorYPosition;
84 si->orig_video_cols = di->CursorMaxXPosition;
85 si->orig_video_lines = di->CursorMaxYPosition;
86 si->orig_video_isVGA = VIDEO_TYPE_VGAC;
87 si->orig_video_points = 16;
88 }
89#endif
90#endif
91}
92
93static struct resource sni_io_resource = {
94 "PCIMT IO MEM", 0x00001000UL, 0x03bfffffUL, IORESOURCE_IO,
95};
96
97static struct resource pcimt_io_resources[] = {
98 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
99 { "timer", 0x40, 0x5f, IORESOURCE_BUSY },
100 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
101 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
102 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
103 { "PCI config data", 0xcfc, 0xcff, IORESOURCE_BUSY }
104};
105
106static struct resource sni_mem_resource = {
107 "PCIMT PCI MEM", 0x10000000UL, 0xffffffffUL, IORESOURCE_MEM
108};
109
110/*
111 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
112 * for other purposes. Be paranoid and allocate all of the before the PCI
113 * code gets a chance to to map anything else there ...
114 *
115 * This leaves the following areas available:
116 *
117 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
118 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
119 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
120 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
121 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
122 */
123static struct resource pcimt_mem_resources[] = {
124 { "Video RAM area", 0x100a0000, 0x100bffff, IORESOURCE_BUSY },
125 { "ISA Reserved", 0x100c0000, 0x100fffff, IORESOURCE_BUSY },
126 { "PCI IO", 0x14000000, 0x17bfffff, IORESOURCE_BUSY },
127 { "Cache Replacement Area", 0x17c00000, 0x17ffffff, IORESOURCE_BUSY},
128 { "PCI INT Acknowledge", 0x1a000000, 0x1a000003, IORESOURCE_BUSY },
129 { "Boot PROM", 0x1fc00000, 0x1fc7ffff, IORESOURCE_BUSY},
130 { "Diag PROM", 0x1fc80000, 0x1fcfffff, IORESOURCE_BUSY},
131 { "X-Bus", 0x1fd00000, 0x1fdfffff, IORESOURCE_BUSY},
132 { "BIOS map", 0x1fe00000, 0x1fefffff, IORESOURCE_BUSY},
133 { "NVRAM / EEPROM", 0x1ff00000, 0x1ff7ffff, IORESOURCE_BUSY},
134 { "ASIC PCI", 0x1fff0000, 0x1fffefff, IORESOURCE_BUSY},
135 { "MP Agent", 0x1ffff000, 0x1fffffff, IORESOURCE_BUSY},
136 { "Main Memory", 0x20000000, 0x9fffffff, IORESOURCE_BUSY}
137};
138
139static void __init sni_resource_init(void)
140{
141 int i;
142
143 /* request I/O space for devices used on all i[345]86 PCs */
144 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
145 request_resource(&ioport_resource, pcimt_io_resources + i);
146
147 /* request mem space for pcimt-specific devices */
148 for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
149 request_resource(&sni_mem_resource, pcimt_mem_resources + i);
150
151 ioport_resource.end = sni_io_resource.end;
152}
153
154extern struct pci_ops sni_pci_ops;
155
156static struct pci_controller sni_controller = {
157 .pci_ops = &sni_pci_ops,
158 .mem_resource = &sni_mem_resource,
159 .mem_offset = 0x10000000UL,
160 .io_resource = &sni_io_resource,
161 .io_offset = 0x00000000UL
162};
163
164static inline void sni_pcimt_time_init(void)
165{
166 rtc_get_time = mc146818_get_cmos_time;
167 rtc_set_time = mc146818_set_rtc_mmss;
168}
169
170static int __init sni_rm200_pci_setup(void)
171{
172 sni_pcimt_detect();
173 sni_pcimt_sc_init();
174 sni_pcimt_time_init();
175
176 set_io_port_base(SNI_PORT_BASE);
177 ioport_resource.end = sni_io_resource.end;
178
179 /*
180 * Setup (E)ISA I/O memory access stuff
181 */
182 isa_slot_offset = 0xb0000000;
183#ifdef CONFIG_EISA
184 EISA_bus = 1;
185#endif
186
187 sni_resource_init();
188 board_timer_setup = sni_rm200_pci_timer_setup;
189
190 _machine_restart = sni_machine_restart;
191 _machine_halt = sni_machine_halt;
192 _machine_power_off = sni_machine_power_off;
193
194 sni_display_setup();
195
196#ifdef CONFIG_PCI
197 register_pci_controller(&sni_controller);
198#endif
199
200 return 0;
201}
202
203early_initcall(sni_rm200_pci_setup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 17:20:51 -0500