diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
commit | 49a89efbbbcc178a39555c43bd59a7593c429664 (patch) | |
tree | 93ab78ec340d3f2fe23f9f853edd0bd62dcc64bb /arch/mips/sni/pcit.c | |
parent | 10cc3529072d5415fb040018a8a99aa7a60190b6 (diff) |
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sni/pcit.c')
-rw-r--r-- | arch/mips/sni/pcit.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index 3361bdd240e6..416f397c768b 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c | |||
@@ -188,8 +188,8 @@ static void pcit_hwint1(void) | |||
188 | irq = ffs((pending >> 16) & 0x7f); | 188 | irq = ffs((pending >> 16) & 0x7f); |
189 | 189 | ||
190 | if (likely(irq > 0)) | 190 | if (likely(irq > 0)) |
191 | do_IRQ (irq + SNI_PCIT_INT_START - 1); | 191 | do_IRQ(irq + SNI_PCIT_INT_START - 1); |
192 | set_c0_status (IE_IRQ1); | 192 | set_c0_status(IE_IRQ1); |
193 | } | 193 | } |
194 | 194 | ||
195 | static void pcit_hwint0(void) | 195 | static void pcit_hwint0(void) |
@@ -201,8 +201,8 @@ static void pcit_hwint0(void) | |||
201 | irq = ffs((pending >> 16) & 0x3f); | 201 | irq = ffs((pending >> 16) & 0x3f); |
202 | 202 | ||
203 | if (likely(irq > 0)) | 203 | if (likely(irq > 0)) |
204 | do_IRQ (irq + SNI_PCIT_INT_START - 1); | 204 | do_IRQ(irq + SNI_PCIT_INT_START - 1); |
205 | set_c0_status (IE_IRQ0); | 205 | set_c0_status(IE_IRQ0); |
206 | } | 206 | } |
207 | 207 | ||
208 | static void sni_pcit_hwint(void) | 208 | static void sni_pcit_hwint(void) |
@@ -212,11 +212,11 @@ static void sni_pcit_hwint(void) | |||
212 | if (pending & C_IRQ1) | 212 | if (pending & C_IRQ1) |
213 | pcit_hwint1(); | 213 | pcit_hwint1(); |
214 | else if (pending & C_IRQ2) | 214 | else if (pending & C_IRQ2) |
215 | do_IRQ (MIPS_CPU_IRQ_BASE + 4); | 215 | do_IRQ(MIPS_CPU_IRQ_BASE + 4); |
216 | else if (pending & C_IRQ3) | 216 | else if (pending & C_IRQ3) |
217 | do_IRQ (MIPS_CPU_IRQ_BASE + 5); | 217 | do_IRQ(MIPS_CPU_IRQ_BASE + 5); |
218 | else if (pending & C_IRQ5) | 218 | else if (pending & C_IRQ5) |
219 | do_IRQ (MIPS_CPU_IRQ_BASE + 7); | 219 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
220 | } | 220 | } |
221 | 221 | ||
222 | static void sni_pcit_hwint_cplus(void) | 222 | static void sni_pcit_hwint_cplus(void) |
@@ -226,13 +226,13 @@ static void sni_pcit_hwint_cplus(void) | |||
226 | if (pending & C_IRQ0) | 226 | if (pending & C_IRQ0) |
227 | pcit_hwint0(); | 227 | pcit_hwint0(); |
228 | else if (pending & C_IRQ1) | 228 | else if (pending & C_IRQ1) |
229 | do_IRQ (MIPS_CPU_IRQ_BASE + 3); | 229 | do_IRQ(MIPS_CPU_IRQ_BASE + 3); |
230 | else if (pending & C_IRQ2) | 230 | else if (pending & C_IRQ2) |
231 | do_IRQ (MIPS_CPU_IRQ_BASE + 4); | 231 | do_IRQ(MIPS_CPU_IRQ_BASE + 4); |
232 | else if (pending & C_IRQ3) | 232 | else if (pending & C_IRQ3) |
233 | do_IRQ (MIPS_CPU_IRQ_BASE + 5); | 233 | do_IRQ(MIPS_CPU_IRQ_BASE + 5); |
234 | else if (pending & C_IRQ5) | 234 | else if (pending & C_IRQ5) |
235 | do_IRQ (MIPS_CPU_IRQ_BASE + 7); | 235 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
236 | } | 236 | } |
237 | 237 | ||
238 | void __init sni_pcit_irq_init(void) | 238 | void __init sni_pcit_irq_init(void) |
@@ -245,7 +245,7 @@ void __init sni_pcit_irq_init(void) | |||
245 | *(volatile u32 *)SNI_PCIT_INT_REG = 0; | 245 | *(volatile u32 *)SNI_PCIT_INT_REG = 0; |
246 | sni_hwint = sni_pcit_hwint; | 246 | sni_hwint = sni_pcit_hwint; |
247 | change_c0_status(ST0_IM, IE_IRQ1); | 247 | change_c0_status(ST0_IM, IE_IRQ1); |
248 | setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); | 248 | setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq); |
249 | } | 249 | } |
250 | 250 | ||
251 | void __init sni_pcit_cplus_irq_init(void) | 251 | void __init sni_pcit_cplus_irq_init(void) |
@@ -258,7 +258,7 @@ void __init sni_pcit_cplus_irq_init(void) | |||
258 | *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; | 258 | *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; |
259 | sni_hwint = sni_pcit_hwint_cplus; | 259 | sni_hwint = sni_pcit_hwint_cplus; |
260 | change_c0_status(ST0_IM, IE_IRQ0); | 260 | change_c0_status(ST0_IM, IE_IRQ0); |
261 | setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); | 261 | setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); |
262 | } | 262 | } |
263 | 263 | ||
264 | void __init sni_pcit_init(void) | 264 | void __init sni_pcit_init(void) |