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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2007-04-08 07:34:57 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-04-27 11:20:25 -0400
commitbea771751c116a690054581902b4144fe5a4520e (patch)
tree50a30896d145bff748071456f34d40bced4cf460 /arch/mips/sni/pcimt.c
parent639702bd725b3cc1a9bd442a7822c83849d66e91 (diff)
[MIPS] Change PCI host bridge setup/resources
PCI host bridge setup for SNI RM machines with PCI is quite broken, now that Linux does it's resource setup own its own. It will use IO addresses, which are needed by the EISA config detection and assigns PCI memory addresses, which overlap with ISA legacy addresses (video ram). Below is a patch, which changes the way how the PCI memory addresses are used and sets the minimum IO address to give enough IO space for 8 EISA slots). This patch needs the other PCI resource change, I've posted. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sni/pcimt.c')
-rw-r--r--arch/mips/sni/pcimt.c105
1 files changed, 10 insertions, 95 deletions
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 8e8593b64f6a..9ee208daa8b1 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -91,7 +91,7 @@ static struct platform_device pcimt_serial8250_device = {
91}; 91};
92 92
93static struct resource sni_io_resource = { 93static struct resource sni_io_resource = {
94 .start = 0x00001000UL, 94 .start = 0x00000000UL,
95 .end = 0x03bfffffUL, 95 .end = 0x03bfffffUL,
96 .name = "PCIMT IO MEM", 96 .name = "PCIMT IO MEM",
97 .flags = IORESOURCE_IO, 97 .flags = IORESOURCE_IO,
@@ -132,107 +132,19 @@ static struct resource pcimt_io_resources[] = {
132}; 132};
133 133
134static struct resource sni_mem_resource = { 134static struct resource sni_mem_resource = {
135 .start = 0x10000000UL, 135 .start = 0x18000000UL,
136 .end = 0xffffffffUL, 136 .end = 0x1fbfffffUL,
137 .name = "PCIMT PCI MEM", 137 .name = "PCIMT PCI MEM",
138 .flags = IORESOURCE_MEM 138 .flags = IORESOURCE_MEM
139}; 139};
140 140
141/*
142 * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
143 * for other purposes. Be paranoid and allocate all of the before the PCI
144 * code gets a chance to to map anything else there ...
145 *
146 * This leaves the following areas available:
147 *
148 * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
149 * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
150 * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
151 * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
152 * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
153 */
154static struct resource pcimt_mem_resources[] = {
155 {
156 .start = 0x100a0000,
157 .end = 0x100bffff,
158 .name = "Video RAM area",
159 .flags = IORESOURCE_BUSY
160 }, {
161 .start = 0x100c0000,
162 .end = 0x100fffff,
163 .name = "ISA Reserved",
164 .flags = IORESOURCE_BUSY
165 }, {
166 .start = 0x14000000,
167 .end = 0x17bfffff,
168 .name = "PCI IO",
169 .flags = IORESOURCE_BUSY
170 }, {
171 .start = 0x17c00000,
172 .end = 0x17ffffff,
173 .name = "Cache Replacement Area",
174 .flags = IORESOURCE_BUSY
175 }, {
176 .start = 0x1a000000,
177 .end = 0x1a000003,
178 .name = "PCI INT Acknowledge",
179 .flags = IORESOURCE_BUSY
180 }, {
181 .start = 0x1fc00000,
182 .end = 0x1fc7ffff,
183 .name = "Boot PROM",
184 .flags = IORESOURCE_BUSY
185 }, {
186 .start = 0x1fc80000,
187 .end = 0x1fcfffff,
188 .name = "Diag PROM",
189 .flags = IORESOURCE_BUSY
190 }, {
191 .start = 0x1fd00000,
192 .end = 0x1fdfffff,
193 .name = "X-Bus",
194 .flags = IORESOURCE_BUSY
195 }, {
196 .start = 0x1fe00000,
197 .end = 0x1fefffff,
198 .name = "BIOS map",
199 .flags = IORESOURCE_BUSY
200 }, {
201 .start = 0x1ff00000,
202 .end = 0x1ff7ffff,
203 .name = "NVRAM / EEPROM",
204 .flags = IORESOURCE_BUSY
205 }, {
206 .start = 0x1fff0000,
207 .end = 0x1fffefff,
208 .name = "ASIC PCI",
209 .flags = IORESOURCE_BUSY
210 }, {
211 .start = 0x1ffff000,
212 .end = 0x1fffffff,
213 .name = "MP Agent",
214 .flags = IORESOURCE_BUSY
215 }, {
216 .start = 0x20000000,
217 .end = 0x9fffffff,
218 .name = "Main Memory",
219 .flags = IORESOURCE_BUSY
220 }
221};
222
223static void __init sni_pcimt_resource_init(void) 141static void __init sni_pcimt_resource_init(void)
224{ 142{
225 int i; 143 int i;
226 144
227 /* request I/O space for devices used on all i[345]86 PCs */ 145 /* request I/O space for devices used on all i[345]86 PCs */
228 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++) 146 for (i = 0; i < ARRAY_SIZE(pcimt_io_resources); i++)
229 request_resource(&ioport_resource, pcimt_io_resources + i); 147 request_resource(&sni_io_resource, pcimt_io_resources + i);
230
231 /* request mem space for pcimt-specific devices */
232 for (i = 0; i < ARRAY_SIZE(pcimt_mem_resources); i++)
233 request_resource(&sni_mem_resource, pcimt_mem_resources + i);
234
235 ioport_resource.end = sni_io_resource.end;
236} 148}
237 149
238extern struct pci_ops sni_pcimt_ops; 150extern struct pci_ops sni_pcimt_ops;
@@ -240,9 +152,10 @@ extern struct pci_ops sni_pcimt_ops;
240static struct pci_controller sni_controller = { 152static struct pci_controller sni_controller = {
241 .pci_ops = &sni_pcimt_ops, 153 .pci_ops = &sni_pcimt_ops,
242 .mem_resource = &sni_mem_resource, 154 .mem_resource = &sni_mem_resource,
243 .mem_offset = 0x10000000UL, 155 .mem_offset = 0x00000000UL,
244 .io_resource = &sni_io_resource, 156 .io_resource = &sni_io_resource,
245 .io_offset = 0x00000000UL 157 .io_offset = 0x00000000UL,
158 .io_map_base = SNI_PORT_BASE
246}; 159};
247 160
248static void enable_pcimt_irq(unsigned int irq) 161static void enable_pcimt_irq(unsigned int irq)
@@ -363,15 +276,17 @@ void __init sni_pcimt_irq_init(void)
363 276
364void sni_pcimt_init(void) 277void sni_pcimt_init(void)
365{ 278{
366 sni_pcimt_resource_init();
367 sni_pcimt_detect(); 279 sni_pcimt_detect();
368 sni_pcimt_sc_init(); 280 sni_pcimt_sc_init();
369 rtc_mips_get_time = mc146818_get_cmos_time; 281 rtc_mips_get_time = mc146818_get_cmos_time;
370 rtc_mips_set_time = mc146818_set_rtc_mmss; 282 rtc_mips_set_time = mc146818_set_rtc_mmss;
371 board_time_init = sni_cpu_time_init; 283 board_time_init = sni_cpu_time_init;
284 ioport_resource.end = sni_io_resource.end;
372#ifdef CONFIG_PCI 285#ifdef CONFIG_PCI
286 PCIBIOS_MIN_IO = 0x9000;
373 register_pci_controller(&sni_controller); 287 register_pci_controller(&sni_controller);
374#endif 288#endif
289 sni_pcimt_resource_init();
375} 290}
376 291
377static int __init snirm_pcimt_setup_devinit(void) 292static int __init snirm_pcimt_setup_devinit(void)