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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 16:44:45 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 16:44:45 -0400
commit8d231c11fd0b694c447e59e687754b6999eea0a2 (patch)
treeb0b3c17efff7018bbf948e489f642c8079f33cc0 /arch/mips/sibyte
parent1f1332f727c3229eb2166a83fec5d3de6a73dce2 (diff)
parent8db089c6b5594c961fb6bc6d613b9926e0d3d98f (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (33 commits) [MIPS] Add missing backslashes to macro definitions. [MIPS] Death list of board support to be removed after 2.6.18. [MIPS] Remove BSD and Sys V compat data types. [MIPS] ioc3.h: Uses u8, so include <linux/types.h>. [MIPS] 74K: Assume it will also have an AR bit in config7 [MIPS] Treat CPUs with AR bit as physically indexed. [MIPS] Oprofile: Support VSMP on 34K. [MIPS] MIPS32/MIPS64 S-cache fix and cleanup [MIPS] excite: PCI makefile needs to use += if it wants a chance to work. [MIPS] excite: plat_setup -> plat_mem_setup. [MIPS] au1xxx: export dbdma functions [MIPS] au1xxx: dbdma, no sleeping under spin_lock [MIPS] au1xxx: fix PSC_SMBTXRX_RSR. [MIPS] Early printk for IP27. [MIPS] Fix handling of 0 length I & D caches. [MIPS] Typo fixes. [MIPS] MIPS32/MIPS64 secondary cache management [MIPS] Fix FIXADDR_TOP for TX39/TX49. [MIPS] Remove first timer interrupt setup in wrppmc_timer_setup() [MIPS] Fix configuration of R2 CPU features and multithreading. ...
Diffstat (limited to 'arch/mips/sibyte')
-rw-r--r--arch/mips/sibyte/Kconfig3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 816aee7fcd25..ec7a2cffacf0 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -3,6 +3,7 @@ config SIBYTE_SB1250
3 select HW_HAS_PCI 3 select HW_HAS_PCI
4 select SIBYTE_HAS_LDT 4 select SIBYTE_HAS_LDT
5 select SIBYTE_SB1xxx_SOC 5 select SIBYTE_SB1xxx_SOC
6 select SYS_SUPPORTS_SMP
6 7
7config SIBYTE_BCM1120 8config SIBYTE_BCM1120
8 bool 9 bool
@@ -30,11 +31,13 @@ config SIBYTE_BCM1x80
30 bool 31 bool
31 select HW_HAS_PCI 32 select HW_HAS_PCI
32 select SIBYTE_SB1xxx_SOC 33 select SIBYTE_SB1xxx_SOC
34 select SYS_SUPPORTS_SMP
33 35
34config SIBYTE_BCM1x55 36config SIBYTE_BCM1x55
35 bool 37 bool
36 select HW_HAS_PCI 38 select HW_HAS_PCI
37 select SIBYTE_SB1xxx_SOC 39 select SIBYTE_SB1xxx_SOC
40 select SYS_SUPPORTS_SMP
38 41
39config SIBYTE_SB1xxx_SOC 42config SIBYTE_SB1xxx_SOC
40 bool 43 bool