diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-03-24 10:26:13 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-03-24 13:01:50 -0400 |
commit | 8fb303c7f1118b0a82aa08e33429adf9b5ad192c (patch) | |
tree | f0da545839b23136dd2dd167125d3c4bef920348 /arch/mips/sibyte | |
parent | 41a8198f61d858bcad7ef705d5d3ec3e3a8dea4a (diff) |
[MIPS] SB1250: Fix bugs/warnings by creative use of volatile.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte')
-rw-r--r-- | arch/mips/sibyte/bcm1480/smp.c | 6 | ||||
-rw-r--r-- | arch/mips/sibyte/swarm/setup.c | 18 |
2 files changed, 13 insertions, 11 deletions
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index bf328277c775..6eac36d1b8c8 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c | |||
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void); | |||
34 | * independent of board/firmware | 34 | * independent of board/firmware |
35 | */ | 35 | */ |
36 | 36 | ||
37 | static volatile void *mailbox_0_set_regs[] = { | 37 | static void *mailbox_0_set_regs[] = { |
38 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 38 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
39 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 39 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
40 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 40 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
41 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 41 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
42 | }; | 42 | }; |
43 | 43 | ||
44 | static volatile void *mailbox_0_clear_regs[] = { | 44 | static void *mailbox_0_clear_regs[] = { |
45 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 45 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
46 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 46 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
47 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 47 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
48 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 48 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
49 | }; | 49 | }; |
50 | 50 | ||
51 | static volatile void *mailbox_0_regs[] = { | 51 | static void *mailbox_0_regs[] = { |
52 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), | 52 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |
53 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), | 53 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |
54 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), | 54 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index defa1f1452ad..83572d8f3e14 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c | |||
@@ -169,17 +169,19 @@ void __init plat_mem_setup(void) | |||
169 | #define LEDS_PHYS MLEDS_PHYS | 169 | #define LEDS_PHYS MLEDS_PHYS |
170 | #endif | 170 | #endif |
171 | 171 | ||
172 | #define setled(index, c) \ | ||
173 | ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c) | ||
174 | void setleds(char *str) | 172 | void setleds(char *str) |
175 | { | 173 | { |
174 | void *reg; | ||
176 | int i; | 175 | int i; |
176 | |||
177 | for (i = 0; i < 4; i++) { | 177 | for (i = 0; i < 4; i++) { |
178 | if (!str[i]) { | 178 | reg = IOADDR(LEDS_PHYS) + 0x20 + ((3 - i) << 3); |
179 | setled(i, ' '); | 179 | |
180 | } else { | 180 | if (!str[i]) |
181 | setled(i, str[i]); | 181 | writeb(' ', reg); |
182 | } | 182 | else |
183 | writeb(str[i], reg); | ||
183 | } | 184 | } |
184 | } | 185 | } |
185 | #endif | 186 | |
187 | #endif /* LEDS_PHYS */ | ||