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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/sibyte
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/sibyte')
-rw-r--r--arch/mips/sibyte/cfe/Makefile3
-rw-r--r--arch/mips/sibyte/cfe/cfe_api.c502
-rw-r--r--arch/mips/sibyte/cfe/cfe_api.h185
-rw-r--r--arch/mips/sibyte/cfe/cfe_api_int.h152
-rw-r--r--arch/mips/sibyte/cfe/cfe_error.h85
-rw-r--r--arch/mips/sibyte/cfe/console.c80
-rw-r--r--arch/mips/sibyte/cfe/setup.c358
-rw-r--r--arch/mips/sibyte/cfe/smp.c92
-rw-r--r--arch/mips/sibyte/sb1250/Makefile8
-rw-r--r--arch/mips/sibyte/sb1250/bcm1250_tbprof.c390
-rw-r--r--arch/mips/sibyte/sb1250/bus_watcher.c259
-rw-r--r--arch/mips/sibyte/sb1250/irq.c431
-rw-r--r--arch/mips/sibyte/sb1250/irq_handler.S147
-rw-r--r--arch/mips/sibyte/sb1250/prom.c98
-rw-r--r--arch/mips/sibyte/sb1250/setup.c206
-rw-r--r--arch/mips/sibyte/sb1250/smp.c98
-rw-r--r--arch/mips/sibyte/sb1250/time.c136
-rw-r--r--arch/mips/sibyte/swarm/Makefile3
-rw-r--r--arch/mips/sibyte/swarm/dbg_io.c76
-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c224
-rw-r--r--arch/mips/sibyte/swarm/rtc_xicor1241.c203
-rw-r--r--arch/mips/sibyte/swarm/setup.c163
-rw-r--r--arch/mips/sibyte/swarm/time.c244
23 files changed, 4143 insertions, 0 deletions
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
new file mode 100644
index 000000000000..059d84a1d8a8
--- /dev/null
+++ b/arch/mips/sibyte/cfe/Makefile
@@ -0,0 +1,3 @@
1lib-y = cfe_api.o setup.o
2lib-$(CONFIG_SMP) += smp.o
3lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
diff --git a/arch/mips/sibyte/cfe/cfe_api.c b/arch/mips/sibyte/cfe/cfe_api.c
new file mode 100644
index 000000000000..c0213605e18a
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_api.c
@@ -0,0 +1,502 @@
1/*
2 * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Device Function stubs File: cfe_api.c
24 *
25 * This module contains device function stubs (small routines to
26 * call the standard "iocb" interface entry point to CFE).
27 * There should be one routine here per iocb function call.
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#include "cfe_api.h"
34#include "cfe_api_int.h"
35
36/* Cast from a native pointer to a cfe_xptr_t and back. */
37#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n))
38#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x))
39
40#ifdef CFE_API_IMPL_NAMESPACE
41#define cfe_iocb_dispatch(a) __cfe_iocb_dispatch(a)
42#endif
43int cfe_iocb_dispatch(cfe_xiocb_t * xiocb);
44
45#if defined(CFE_API_common) || defined(CFE_API_ALL)
46/*
47 * Declare the dispatch function with args of "intptr_t".
48 * This makes sure whatever model we're compiling in
49 * puts the pointers in a single register. For example,
50 * combining -mlong64 and -mips1 or -mips2 would lead to
51 * trouble, since the handle and IOCB pointer will be
52 * passed in two registers each, and CFE expects one.
53 */
54
55static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb) = 0;
56static cfe_xuint_t cfe_handle = 0;
57
58int cfe_init(cfe_xuint_t handle, cfe_xuint_t ept)
59{
60 cfe_dispfunc = NATIVE_FROM_XPTR(ept);
61 cfe_handle = handle;
62 return 0;
63}
64
65int cfe_iocb_dispatch(cfe_xiocb_t * xiocb)
66{
67 if (!cfe_dispfunc)
68 return -1;
69 return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb);
70}
71#endif /* CFE_API_common || CFE_API_ALL */
72
73#if defined(CFE_API_close) || defined(CFE_API_ALL)
74int cfe_close(int handle)
75{
76 cfe_xiocb_t xiocb;
77
78 xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
79 xiocb.xiocb_status = 0;
80 xiocb.xiocb_handle = handle;
81 xiocb.xiocb_flags = 0;
82 xiocb.xiocb_psize = 0;
83
84 cfe_iocb_dispatch(&xiocb);
85
86 return xiocb.xiocb_status;
87
88}
89#endif /* CFE_API_close || CFE_API_ALL */
90
91#if defined(CFE_API_cpu_start) || defined(CFE_API_ALL)
92int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
93{
94 cfe_xiocb_t xiocb;
95
96 xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
97 xiocb.xiocb_status = 0;
98 xiocb.xiocb_handle = 0;
99 xiocb.xiocb_flags = 0;
100 xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
101 xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
102 xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
103 xiocb.plist.xiocb_cpuctl.gp_val = gp;
104 xiocb.plist.xiocb_cpuctl.sp_val = sp;
105 xiocb.plist.xiocb_cpuctl.a1_val = a1;
106 xiocb.plist.xiocb_cpuctl.start_addr = (long) fn;
107
108 cfe_iocb_dispatch(&xiocb);
109
110 return xiocb.xiocb_status;
111}
112#endif /* CFE_API_cpu_start || CFE_API_ALL */
113
114#if defined(CFE_API_cpu_stop) || defined(CFE_API_ALL)
115int cfe_cpu_stop(int cpu)
116{
117 cfe_xiocb_t xiocb;
118
119 xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
120 xiocb.xiocb_status = 0;
121 xiocb.xiocb_handle = 0;
122 xiocb.xiocb_flags = 0;
123 xiocb.xiocb_psize = sizeof(xiocb_cpuctl_t);
124 xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
125 xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
126
127 cfe_iocb_dispatch(&xiocb);
128
129 return xiocb.xiocb_status;
130}
131#endif /* CFE_API_cpu_stop || CFE_API_ALL */
132
133#if defined(CFE_API_enumenv) || defined(CFE_API_ALL)
134int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
135{
136 cfe_xiocb_t xiocb;
137
138 xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
139 xiocb.xiocb_status = 0;
140 xiocb.xiocb_handle = 0;
141 xiocb.xiocb_flags = 0;
142 xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
143 xiocb.plist.xiocb_envbuf.enum_idx = idx;
144 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
145 xiocb.plist.xiocb_envbuf.name_length = namelen;
146 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
147 xiocb.plist.xiocb_envbuf.val_length = vallen;
148
149 cfe_iocb_dispatch(&xiocb);
150
151 return xiocb.xiocb_status;
152}
153#endif /* CFE_API_enumenv || CFE_API_ALL */
154
155#if defined(CFE_API_enummem) || defined(CFE_API_ALL)
156int
157cfe_enummem(int idx, int flags, cfe_xuint_t * start, cfe_xuint_t * length,
158 cfe_xuint_t * type)
159{
160 cfe_xiocb_t xiocb;
161
162 xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
163 xiocb.xiocb_status = 0;
164 xiocb.xiocb_handle = 0;
165 xiocb.xiocb_flags = flags;
166 xiocb.xiocb_psize = sizeof(xiocb_meminfo_t);
167 xiocb.plist.xiocb_meminfo.mi_idx = idx;
168
169 cfe_iocb_dispatch(&xiocb);
170
171 if (xiocb.xiocb_status < 0)
172 return xiocb.xiocb_status;
173
174 *start = xiocb.plist.xiocb_meminfo.mi_addr;
175 *length = xiocb.plist.xiocb_meminfo.mi_size;
176 *type = xiocb.plist.xiocb_meminfo.mi_type;
177
178 return 0;
179}
180#endif /* CFE_API_enummem || CFE_API_ALL */
181
182#if defined(CFE_API_exit) || defined(CFE_API_ALL)
183int cfe_exit(int warm, int status)
184{
185 cfe_xiocb_t xiocb;
186
187 xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
188 xiocb.xiocb_status = 0;
189 xiocb.xiocb_handle = 0;
190 xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
191 xiocb.xiocb_psize = sizeof(xiocb_exitstat_t);
192 xiocb.plist.xiocb_exitstat.status = status;
193
194 cfe_iocb_dispatch(&xiocb);
195
196 return xiocb.xiocb_status;
197}
198#endif /* CFE_API_exit || CFE_API_ALL */
199
200#if defined(CFE_API_flushcache) || defined(CFE_API_ALL)
201int cfe_flushcache(int flg)
202{
203 cfe_xiocb_t xiocb;
204
205 xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
206 xiocb.xiocb_status = 0;
207 xiocb.xiocb_handle = 0;
208 xiocb.xiocb_flags = flg;
209 xiocb.xiocb_psize = 0;
210
211 cfe_iocb_dispatch(&xiocb);
212
213 return xiocb.xiocb_status;
214}
215#endif /* CFE_API_flushcache || CFE_API_ALL */
216
217#if defined(CFE_API_getdevinfo) || defined(CFE_API_ALL)
218int cfe_getdevinfo(char *name)
219{
220 cfe_xiocb_t xiocb;
221
222 xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO;
223 xiocb.xiocb_status = 0;
224 xiocb.xiocb_handle = 0;
225 xiocb.xiocb_flags = 0;
226 xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
227 xiocb.plist.xiocb_buffer.buf_offset = 0;
228 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
229 xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
230
231 cfe_iocb_dispatch(&xiocb);
232
233 if (xiocb.xiocb_status < 0)
234 return xiocb.xiocb_status;
235 return xiocb.plist.xiocb_buffer.buf_devflags;
236}
237#endif /* CFE_API_getdevinfo || CFE_API_ALL */
238
239#if defined(CFE_API_getenv) || defined(CFE_API_ALL)
240int cfe_getenv(char *name, char *dest, int destlen)
241{
242 cfe_xiocb_t xiocb;
243
244 *dest = 0;
245
246 xiocb.xiocb_fcode = CFE_CMD_ENV_GET;
247 xiocb.xiocb_status = 0;
248 xiocb.xiocb_handle = 0;
249 xiocb.xiocb_flags = 0;
250 xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
251 xiocb.plist.xiocb_envbuf.enum_idx = 0;
252 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
253 xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
254 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest);
255 xiocb.plist.xiocb_envbuf.val_length = destlen;
256
257 cfe_iocb_dispatch(&xiocb);
258
259 return xiocb.xiocb_status;
260}
261#endif /* CFE_API_getenv || CFE_API_ALL */
262
263#if defined(CFE_API_getfwinfo) || defined(CFE_API_ALL)
264int cfe_getfwinfo(cfe_fwinfo_t * info)
265{
266 cfe_xiocb_t xiocb;
267
268 xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO;
269 xiocb.xiocb_status = 0;
270 xiocb.xiocb_handle = 0;
271 xiocb.xiocb_flags = 0;
272 xiocb.xiocb_psize = sizeof(xiocb_fwinfo_t);
273
274 cfe_iocb_dispatch(&xiocb);
275
276 if (xiocb.xiocb_status < 0)
277 return xiocb.xiocb_status;
278
279 info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version;
280 info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem;
281 info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags;
282 info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid;
283 info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va;
284 info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa;
285 info->fwi_bootarea_size =
286 xiocb.plist.xiocb_fwinfo.fwi_bootarea_size;
287#if 0
288 info->fwi_reserved1 = xiocb.plist.xiocb_fwinfo.fwi_reserved1;
289 info->fwi_reserved2 = xiocb.plist.xiocb_fwinfo.fwi_reserved2;
290 info->fwi_reserved3 = xiocb.plist.xiocb_fwinfo.fwi_reserved3;
291#endif
292
293 return 0;
294}
295#endif /* CFE_API_getfwinfo || CFE_API_ALL */
296
297#if defined(CFE_API_getstdhandle) || defined(CFE_API_ALL)
298int cfe_getstdhandle(int flg)
299{
300 cfe_xiocb_t xiocb;
301
302 xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
303 xiocb.xiocb_status = 0;
304 xiocb.xiocb_handle = 0;
305 xiocb.xiocb_flags = flg;
306 xiocb.xiocb_psize = 0;
307
308 cfe_iocb_dispatch(&xiocb);
309
310 if (xiocb.xiocb_status < 0)
311 return xiocb.xiocb_status;
312 return xiocb.xiocb_handle;
313}
314#endif /* CFE_API_getstdhandle || CFE_API_ALL */
315
316#if defined(CFE_API_getticks) || defined(CFE_API_ALL)
317int64_t
318#ifdef CFE_API_IMPL_NAMESPACE
319__cfe_getticks(void)
320#else
321cfe_getticks(void)
322#endif
323{
324 cfe_xiocb_t xiocb;
325
326 xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
327 xiocb.xiocb_status = 0;
328 xiocb.xiocb_handle = 0;
329 xiocb.xiocb_flags = 0;
330 xiocb.xiocb_psize = sizeof(xiocb_time_t);
331 xiocb.plist.xiocb_time.ticks = 0;
332
333 cfe_iocb_dispatch(&xiocb);
334
335 return xiocb.plist.xiocb_time.ticks;
336
337}
338#endif /* CFE_API_getticks || CFE_API_ALL */
339
340#if defined(CFE_API_inpstat) || defined(CFE_API_ALL)
341int cfe_inpstat(int handle)
342{
343 cfe_xiocb_t xiocb;
344
345 xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
346 xiocb.xiocb_status = 0;
347 xiocb.xiocb_handle = handle;
348 xiocb.xiocb_flags = 0;
349 xiocb.xiocb_psize = sizeof(xiocb_inpstat_t);
350 xiocb.plist.xiocb_inpstat.inp_status = 0;
351
352 cfe_iocb_dispatch(&xiocb);
353
354 if (xiocb.xiocb_status < 0)
355 return xiocb.xiocb_status;
356 return xiocb.plist.xiocb_inpstat.inp_status;
357}
358#endif /* CFE_API_inpstat || CFE_API_ALL */
359
360#if defined(CFE_API_ioctl) || defined(CFE_API_ALL)
361int
362cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
363 int length, int *retlen, cfe_xuint_t offset)
364{
365 cfe_xiocb_t xiocb;
366
367 xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
368 xiocb.xiocb_status = 0;
369 xiocb.xiocb_handle = handle;
370 xiocb.xiocb_flags = 0;
371 xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
372 xiocb.plist.xiocb_buffer.buf_offset = offset;
373 xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum;
374 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
375 xiocb.plist.xiocb_buffer.buf_length = length;
376
377 cfe_iocb_dispatch(&xiocb);
378
379 if (retlen)
380 *retlen = xiocb.plist.xiocb_buffer.buf_retlen;
381 return xiocb.xiocb_status;
382}
383#endif /* CFE_API_ioctl || CFE_API_ALL */
384
385#if defined(CFE_API_open) || defined(CFE_API_ALL)
386int cfe_open(char *name)
387{
388 cfe_xiocb_t xiocb;
389
390 xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
391 xiocb.xiocb_status = 0;
392 xiocb.xiocb_handle = 0;
393 xiocb.xiocb_flags = 0;
394 xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
395 xiocb.plist.xiocb_buffer.buf_offset = 0;
396 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
397 xiocb.plist.xiocb_buffer.buf_length = cfe_strlen(name);
398
399 cfe_iocb_dispatch(&xiocb);
400
401 if (xiocb.xiocb_status < 0)
402 return xiocb.xiocb_status;
403 return xiocb.xiocb_handle;
404}
405#endif /* CFE_API_open || CFE_API_ALL */
406
407#if defined(CFE_API_read) || defined(CFE_API_ALL)
408int cfe_read(int handle, unsigned char *buffer, int length)
409{
410 return cfe_readblk(handle, 0, buffer, length);
411}
412#endif /* CFE_API_read || CFE_API_ALL */
413
414#if defined(CFE_API_readblk) || defined(CFE_API_ALL)
415int
416cfe_readblk(int handle, cfe_xint_t offset, unsigned char *buffer,
417 int length)
418{
419 cfe_xiocb_t xiocb;
420
421 xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
422 xiocb.xiocb_status = 0;
423 xiocb.xiocb_handle = handle;
424 xiocb.xiocb_flags = 0;
425 xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
426 xiocb.plist.xiocb_buffer.buf_offset = offset;
427 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
428 xiocb.plist.xiocb_buffer.buf_length = length;
429
430 cfe_iocb_dispatch(&xiocb);
431
432 if (xiocb.xiocb_status < 0)
433 return xiocb.xiocb_status;
434 return xiocb.plist.xiocb_buffer.buf_retlen;
435}
436#endif /* CFE_API_readblk || CFE_API_ALL */
437
438#if defined(CFE_API_setenv) || defined(CFE_API_ALL)
439int cfe_setenv(char *name, char *val)
440{
441 cfe_xiocb_t xiocb;
442
443 xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
444 xiocb.xiocb_status = 0;
445 xiocb.xiocb_handle = 0;
446 xiocb.xiocb_flags = 0;
447 xiocb.xiocb_psize = sizeof(xiocb_envbuf_t);
448 xiocb.plist.xiocb_envbuf.enum_idx = 0;
449 xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
450 xiocb.plist.xiocb_envbuf.name_length = cfe_strlen(name);
451 xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
452 xiocb.plist.xiocb_envbuf.val_length = cfe_strlen(val);
453
454 cfe_iocb_dispatch(&xiocb);
455
456 return xiocb.xiocb_status;
457}
458#endif /* CFE_API_setenv || CFE_API_ALL */
459
460#if (defined(CFE_API_strlen) || defined(CFE_API_ALL)) \
461 && !defined(CFE_API_STRLEN_CUSTOM)
462int cfe_strlen(char *name)
463{
464 int count = 0;
465
466 while (*name++)
467 count++;
468
469 return count;
470}
471#endif /* CFE_API_strlen || CFE_API_ALL */
472
473#if defined(CFE_API_write) || defined(CFE_API_ALL)
474int cfe_write(int handle, unsigned char *buffer, int length)
475{
476 return cfe_writeblk(handle, 0, buffer, length);
477}
478#endif /* CFE_API_write || CFE_API_ALL */
479
480#if defined(CFE_API_writeblk) || defined(CFE_API_ALL)
481int
482cfe_writeblk(int handle, cfe_xint_t offset, unsigned char *buffer,
483 int length)
484{
485 cfe_xiocb_t xiocb;
486
487 xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
488 xiocb.xiocb_status = 0;
489 xiocb.xiocb_handle = handle;
490 xiocb.xiocb_flags = 0;
491 xiocb.xiocb_psize = sizeof(xiocb_buffer_t);
492 xiocb.plist.xiocb_buffer.buf_offset = offset;
493 xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
494 xiocb.plist.xiocb_buffer.buf_length = length;
495
496 cfe_iocb_dispatch(&xiocb);
497
498 if (xiocb.xiocb_status < 0)
499 return xiocb.xiocb_status;
500 return xiocb.plist.xiocb_buffer.buf_retlen;
501}
502#endif /* CFE_API_writeblk || CFE_API_ALL */
diff --git a/arch/mips/sibyte/cfe/cfe_api.h b/arch/mips/sibyte/cfe/cfe_api.h
new file mode 100644
index 000000000000..d8230cc53b81
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_api.h
@@ -0,0 +1,185 @@
1/*
2 * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Device function prototypes File: cfe_api.h
24 *
25 * This file contains declarations for doing callbacks to
26 * cfe from an application. It should be the only header
27 * needed by the application to use this library
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#ifndef CFE_API_H
34#define CFE_API_H
35
36/*
37 * Apply customizations here for different OSes. These need to:
38 * * typedef uint64_t, int64_t, intptr_t, uintptr_t.
39 * * define cfe_strlen() if use of an existing function is desired.
40 * * define CFE_API_IMPL_NAMESPACE if API functions are to use
41 * names in the implementation namespace.
42 * Also, optionally, if the build environment does not do so automatically,
43 * CFE_API_* can be defined here as desired.
44 */
45/* Begin customization. */
46#include <linux/types.h>
47#include <linux/string.h>
48
49typedef long intptr_t;
50
51#define cfe_strlen strlen
52
53#define CFE_API_ALL
54#define CFE_API_STRLEN_CUSTOM
55/* End customization. */
56
57
58/* *********************************************************************
59 * Constants
60 ********************************************************************* */
61
62/* Seal indicating CFE's presence, passed to user program. */
63#define CFE_EPTSEAL 0x43464531
64
65#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
66#define CFE_MI_AVAILABLE 1 /* memory is available */
67
68#define CFE_FLG_WARMSTART 0x00000001
69#define CFE_FLG_FULL_ARENA 0x00000001
70#define CFE_FLG_ENV_PERMANENT 0x00000001
71
72#define CFE_CPU_CMD_START 1
73#define CFE_CPU_CMD_STOP 0
74
75#define CFE_STDHANDLE_CONSOLE 0
76
77#define CFE_DEV_NETWORK 1
78#define CFE_DEV_DISK 2
79#define CFE_DEV_FLASH 3
80#define CFE_DEV_SERIAL 4
81#define CFE_DEV_CPU 5
82#define CFE_DEV_NVRAM 6
83#define CFE_DEV_CLOCK 7
84#define CFE_DEV_OTHER 8
85#define CFE_DEV_MASK 0x0F
86
87#define CFE_CACHE_FLUSH_D 1
88#define CFE_CACHE_INVAL_I 2
89#define CFE_CACHE_INVAL_D 4
90#define CFE_CACHE_INVAL_L2 8
91
92#define CFE_FWI_64BIT 0x00000001
93#define CFE_FWI_32BIT 0x00000002
94#define CFE_FWI_RELOC 0x00000004
95#define CFE_FWI_UNCACHED 0x00000008
96#define CFE_FWI_MULTICPU 0x00000010
97#define CFE_FWI_FUNCSIM 0x00000020
98#define CFE_FWI_RTLSIM 0x00000040
99
100typedef struct {
101 int64_t fwi_version; /* major, minor, eco version */
102 int64_t fwi_totalmem; /* total installed mem */
103 int64_t fwi_flags; /* various flags */
104 int64_t fwi_boardid; /* board ID */
105 int64_t fwi_bootarea_va; /* VA of boot area */
106 int64_t fwi_bootarea_pa; /* PA of boot area */
107 int64_t fwi_bootarea_size; /* size of boot area */
108} cfe_fwinfo_t;
109
110
111/*
112 * cfe_strlen is handled specially: If already defined, it has been
113 * overridden in this environment with a standard strlen-like function.
114 */
115#ifdef cfe_strlen
116# define CFE_API_STRLEN_CUSTOM
117#else
118# ifdef CFE_API_IMPL_NAMESPACE
119# define cfe_strlen(a) __cfe_strlen(a)
120# endif
121int cfe_strlen(char *name);
122#endif
123
124/*
125 * Defines and prototypes for functions which take no arguments.
126 */
127#ifdef CFE_API_IMPL_NAMESPACE
128int64_t __cfe_getticks(void);
129#define cfe_getticks() __cfe_getticks()
130#else
131int64_t cfe_getticks(void);
132#endif
133
134/*
135 * Defines and prototypes for the rest of the functions.
136 */
137#ifdef CFE_API_IMPL_NAMESPACE
138#define cfe_close(a) __cfe_close(a)
139#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e)
140#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
141#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f)
142#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e)
143#define cfe_exit(a,b) __cfe_exit(a,b)
144#define cfe_flushcache(a) __cfe_cacheflush(a)
145#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
146#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c)
147#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
148#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
149#define cfe_init(a,b) __cfe_init(a,b)
150#define cfe_inpstat(a) __cfe_inpstat(a)
151#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f)
152#define cfe_open(a) __cfe_open(a)
153#define cfe_read(a,b,c) __cfe_read(a,b,c)
154#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d)
155#define cfe_setenv(a,b) __cfe_setenv(a,b)
156#define cfe_write(a,b,c) __cfe_write(a,b,c)
157#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d)
158#endif /* CFE_API_IMPL_NAMESPACE */
159
160int cfe_close(int handle);
161int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
162int cfe_cpu_stop(int cpu);
163int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
164int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
165 uint64_t * type);
166int cfe_exit(int warm, int status);
167int cfe_flushcache(int flg);
168int cfe_getdevinfo(char *name);
169int cfe_getenv(char *name, char *dest, int destlen);
170int cfe_getfwinfo(cfe_fwinfo_t * info);
171int cfe_getstdhandle(int flg);
172int cfe_init(uint64_t handle, uint64_t ept);
173int cfe_inpstat(int handle);
174int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
175 int length, int *retlen, uint64_t offset);
176int cfe_open(char *name);
177int cfe_read(int handle, unsigned char *buffer, int length);
178int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
179 int length);
180int cfe_setenv(char *name, char *val);
181int cfe_write(int handle, unsigned char *buffer, int length);
182int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
183 int length);
184
185#endif /* CFE_API_H */
diff --git a/arch/mips/sibyte/cfe/cfe_api_int.h b/arch/mips/sibyte/cfe/cfe_api_int.h
new file mode 100644
index 000000000000..f7e5a64b55f3
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_api_int.h
@@ -0,0 +1,152 @@
1/*
2 * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Device function prototypes File: cfe_api_int.h
24 *
25 * This header defines all internal types and macros for the
26 * library. This is stuff that's not exported to an app
27 * using the library.
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#ifndef CFE_API_INT_H
34#define CFE_API_INT_H
35
36/* *********************************************************************
37 * Constants
38 ********************************************************************* */
39
40#define CFE_CMD_FW_GETINFO 0
41#define CFE_CMD_FW_RESTART 1
42#define CFE_CMD_FW_BOOT 2
43#define CFE_CMD_FW_CPUCTL 3
44#define CFE_CMD_FW_GETTIME 4
45#define CFE_CMD_FW_MEMENUM 5
46#define CFE_CMD_FW_FLUSHCACHE 6
47
48#define CFE_CMD_DEV_GETHANDLE 9
49#define CFE_CMD_DEV_ENUM 10
50#define CFE_CMD_DEV_OPEN 11
51#define CFE_CMD_DEV_INPSTAT 12
52#define CFE_CMD_DEV_READ 13
53#define CFE_CMD_DEV_WRITE 14
54#define CFE_CMD_DEV_IOCTL 15
55#define CFE_CMD_DEV_CLOSE 16
56#define CFE_CMD_DEV_GETINFO 17
57
58#define CFE_CMD_ENV_ENUM 20
59#define CFE_CMD_ENV_GET 22
60#define CFE_CMD_ENV_SET 23
61#define CFE_CMD_ENV_DEL 24
62
63#define CFE_CMD_MAX 32
64
65#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
66
67/* *********************************************************************
68 * Structures
69 ********************************************************************* */
70
71typedef uint64_t cfe_xuint_t;
72typedef int64_t cfe_xint_t;
73typedef int64_t cfe_xptr_t;
74
75typedef struct xiocb_buffer_s {
76 cfe_xuint_t buf_offset; /* offset on device (bytes) */
77 cfe_xptr_t buf_ptr; /* pointer to a buffer */
78 cfe_xuint_t buf_length; /* length of this buffer */
79 cfe_xuint_t buf_retlen; /* returned length (for read ops) */
80 cfe_xuint_t buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
81} xiocb_buffer_t;
82
83#define buf_devflags buf_ioctlcmd /* returned device info flags */
84
85typedef struct xiocb_inpstat_s {
86 cfe_xuint_t inp_status; /* 1 means input available */
87} xiocb_inpstat_t;
88
89typedef struct xiocb_envbuf_s {
90 cfe_xint_t enum_idx; /* 0-based enumeration index */
91 cfe_xptr_t name_ptr; /* name string buffer */
92 cfe_xint_t name_length; /* size of name buffer */
93 cfe_xptr_t val_ptr; /* value string buffer */
94 cfe_xint_t val_length; /* size of value string buffer */
95} xiocb_envbuf_t;
96
97typedef struct xiocb_cpuctl_s {
98 cfe_xuint_t cpu_number; /* cpu number to control */
99 cfe_xuint_t cpu_command; /* command to issue to CPU */
100 cfe_xuint_t start_addr; /* CPU start address */
101 cfe_xuint_t gp_val; /* starting GP value */
102 cfe_xuint_t sp_val; /* starting SP value */
103 cfe_xuint_t a1_val; /* starting A1 value */
104} xiocb_cpuctl_t;
105
106typedef struct xiocb_time_s {
107 cfe_xint_t ticks; /* current time in ticks */
108} xiocb_time_t;
109
110typedef struct xiocb_exitstat_s {
111 cfe_xint_t status;
112} xiocb_exitstat_t;
113
114typedef struct xiocb_meminfo_s {
115 cfe_xint_t mi_idx; /* 0-based enumeration index */
116 cfe_xint_t mi_type; /* type of memory block */
117 cfe_xuint_t mi_addr; /* physical start address */
118 cfe_xuint_t mi_size; /* block size */
119} xiocb_meminfo_t;
120
121typedef struct xiocb_fwinfo_s {
122 cfe_xint_t fwi_version; /* major, minor, eco version */
123 cfe_xint_t fwi_totalmem; /* total installed mem */
124 cfe_xint_t fwi_flags; /* various flags */
125 cfe_xint_t fwi_boardid; /* board ID */
126 cfe_xint_t fwi_bootarea_va; /* VA of boot area */
127 cfe_xint_t fwi_bootarea_pa; /* PA of boot area */
128 cfe_xint_t fwi_bootarea_size; /* size of boot area */
129 cfe_xint_t fwi_reserved1;
130 cfe_xint_t fwi_reserved2;
131 cfe_xint_t fwi_reserved3;
132} xiocb_fwinfo_t;
133
134typedef struct cfe_xiocb_s {
135 cfe_xuint_t xiocb_fcode; /* IOCB function code */
136 cfe_xint_t xiocb_status; /* return status */
137 cfe_xint_t xiocb_handle; /* file/device handle */
138 cfe_xuint_t xiocb_flags; /* flags for this IOCB */
139 cfe_xuint_t xiocb_psize; /* size of parameter list */
140 union {
141 xiocb_buffer_t xiocb_buffer; /* buffer parameters */
142 xiocb_inpstat_t xiocb_inpstat; /* input status parameters */
143 xiocb_envbuf_t xiocb_envbuf; /* environment function parameters */
144 xiocb_cpuctl_t xiocb_cpuctl; /* CPU control parameters */
145 xiocb_time_t xiocb_time; /* timer parameters */
146 xiocb_meminfo_t xiocb_meminfo; /* memory arena info parameters */
147 xiocb_fwinfo_t xiocb_fwinfo; /* firmware information */
148 xiocb_exitstat_t xiocb_exitstat; /* Exit Status */
149 } plist;
150} cfe_xiocb_t;
151
152#endif /* CFE_API_INT_H */
diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h
new file mode 100644
index 000000000000..77eb4935bfb4
--- /dev/null
+++ b/arch/mips/sibyte/cfe/cfe_error.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Error codes File: cfe_error.h
24 *
25 * CFE's global error code list is here.
26 *
27 * Author: Mitch Lichtenberg
28 *
29 ********************************************************************* */
30
31
32#define CFE_OK 0
33#define CFE_ERR -1 /* generic error */
34#define CFE_ERR_INV_COMMAND -2
35#define CFE_ERR_EOF -3
36#define CFE_ERR_IOERR -4
37#define CFE_ERR_NOMEM -5
38#define CFE_ERR_DEVNOTFOUND -6
39#define CFE_ERR_DEVOPEN -7
40#define CFE_ERR_INV_PARAM -8
41#define CFE_ERR_ENVNOTFOUND -9
42#define CFE_ERR_ENVREADONLY -10
43
44#define CFE_ERR_NOTELF -11
45#define CFE_ERR_NOT32BIT -12
46#define CFE_ERR_WRONGENDIAN -13
47#define CFE_ERR_BADELFVERS -14
48#define CFE_ERR_NOTMIPS -15
49#define CFE_ERR_BADELFFMT -16
50#define CFE_ERR_BADADDR -17
51
52#define CFE_ERR_FILENOTFOUND -18
53#define CFE_ERR_UNSUPPORTED -19
54
55#define CFE_ERR_HOSTUNKNOWN -20
56
57#define CFE_ERR_TIMEOUT -21
58
59#define CFE_ERR_PROTOCOLERR -22
60
61#define CFE_ERR_NETDOWN -23
62#define CFE_ERR_NONAMESERVER -24
63
64#define CFE_ERR_NOHANDLES -25
65#define CFE_ERR_ALREADYBOUND -26
66
67#define CFE_ERR_CANNOTSET -27
68#define CFE_ERR_NOMORE -28
69#define CFE_ERR_BADFILESYS -29
70#define CFE_ERR_FSNOTAVAIL -30
71
72#define CFE_ERR_INVBOOTBLOCK -31
73#define CFE_ERR_WRONGDEVTYPE -32
74#define CFE_ERR_BBCHECKSUM -33
75#define CFE_ERR_BOOTPROGCHKSUM -34
76
77#define CFE_ERR_LDRNOTAVAIL -35
78
79#define CFE_ERR_NOTREADY -36
80
81#define CFE_ERR_GETMEM -37
82#define CFE_ERR_SETMEM -38
83
84#define CFE_ERR_NOTCONN -39
85#define CFE_ERR_ADDRINUSE -40
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
new file mode 100644
index 000000000000..53a5c1eb5611
--- /dev/null
+++ b/arch/mips/sibyte/cfe/console.c
@@ -0,0 +1,80 @@
1#include <linux/config.h>
2#include <linux/init.h>
3#include <linux/errno.h>
4#include <linux/console.h>
5
6#include <asm/sibyte/board.h>
7
8#include "cfe_api.h"
9#include "cfe_error.h"
10
11extern int cfe_cons_handle;
12
13static void cfe_console_write(struct console *cons, const char *str,
14 unsigned int count)
15{
16 int i, last, written;
17
18 for (i=0,last=0; i<count; i++) {
19 if (!str[i])
20 /* XXXKW can/should this ever happen? */
21 return;
22 if (str[i] == '\n') {
23 do {
24 written = cfe_write(cfe_cons_handle, &str[last], i-last);
25 if (written < 0)
26 ;
27 last += written;
28 } while (last < i);
29 while (cfe_write(cfe_cons_handle, "\r", 1) <= 0)
30 ;
31 }
32 }
33 if (last != count) {
34 do {
35 written = cfe_write(cfe_cons_handle, &str[last], count-last);
36 if (written < 0)
37 ;
38 last += written;
39 } while (last < count);
40 }
41
42}
43
44static int cfe_console_setup(struct console *cons, char *str)
45{
46 char consdev[32];
47 /* XXXKW think about interaction with 'console=' cmdline arg */
48 /* If none of the console options are configured, the build will break. */
49 if (cfe_getenv("BOOT_CONSOLE", consdev, 32) >= 0) {
50#ifdef CONFIG_SIBYTE_SB1250_DUART
51 if (!strcmp(consdev, "uart0")) {
52 setleds("u0cn");
53 } else if (!strcmp(consdev, "uart1")) {
54 setleds("u1cn");
55#endif
56#ifdef CONFIG_VGA_CONSOLE
57 } else if (!strcmp(consdev, "pcconsole0")) {
58 setleds("pccn");
59#endif
60 } else
61 return -ENODEV;
62 }
63 return 0;
64}
65
66static struct console sb1250_cfe_cons = {
67 .name = "cfe",
68 .write = cfe_console_write,
69 .setup = cfe_console_setup,
70 .flags = CON_PRINTBUFFER,
71 .index = -1,
72};
73
74static int __init sb1250_cfe_console_init(void)
75{
76 register_console(&sb1250_cfe_cons);
77 return 0;
78}
79
80console_initcall(sb1250_cfe_console_init);
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
new file mode 100644
index 000000000000..d6d0364fa760
--- /dev/null
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -0,0 +1,358 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/linkage.h>
23#include <linux/mm.h>
24#include <linux/blkdev.h>
25#include <linux/bootmem.h>
26#include <linux/smp.h>
27
28#include <asm/bootinfo.h>
29#include <asm/reboot.h>
30#include <asm/sibyte/board.h>
31
32#include "cfe_api.h"
33#include "cfe_error.h"
34
35/* Max ram addressable in 32-bit segments */
36#ifdef CONFIG_MIPS64
37#define MAX_RAM_SIZE (~0ULL)
38#else
39#ifdef CONFIG_HIGHMEM
40#ifdef CONFIG_64BIT_PHYS_ADDR
41#define MAX_RAM_SIZE (~0ULL)
42#else
43#define MAX_RAM_SIZE (0xffffffffULL)
44#endif
45#else
46#define MAX_RAM_SIZE (0x1fffffffULL)
47#endif
48#endif
49
50#define SIBYTE_MAX_MEM_REGIONS 8
51phys_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS];
52phys_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS];
53unsigned int board_mem_region_count;
54
55int cfe_cons_handle;
56
57#ifdef CONFIG_BLK_DEV_INITRD
58extern unsigned long initrd_start, initrd_end;
59#endif
60
61#ifdef CONFIG_KGDB
62extern int kgdb_port;
63#endif
64
65static void ATTRIB_NORET cfe_linux_exit(void *arg)
66{
67 int warm = *(int *)arg;
68
69 if (smp_processor_id()) {
70 static int reboot_smp;
71
72 /* Don't repeat the process from another CPU */
73 if (!reboot_smp) {
74 /* Get CPU 0 to do the cfe_exit */
75 reboot_smp = 1;
76 smp_call_function(cfe_linux_exit, arg, 1, 0);
77 }
78 } else {
79 printk("Passing control back to CFE...\n");
80 cfe_exit(warm, 0);
81 printk("cfe_exit returned??\n");
82 }
83 while (1);
84}
85
86static void ATTRIB_NORET cfe_linux_restart(char *command)
87{
88 static const int zero;
89
90 cfe_linux_exit((void *)&zero);
91}
92
93static void ATTRIB_NORET cfe_linux_halt(void)
94{
95 static const int one = 1;
96
97 cfe_linux_exit((void *)&one);
98}
99
100static __init void prom_meminit(void)
101{
102 u64 addr, size, type; /* regardless of 64BIT_PHYS_ADDR */
103 int mem_flags = 0;
104 unsigned int idx;
105 int rd_flag;
106#ifdef CONFIG_BLK_DEV_INITRD
107 unsigned long initrd_pstart;
108 unsigned long initrd_pend;
109
110 initrd_pstart = CPHYSADDR(initrd_start);
111 initrd_pend = CPHYSADDR(initrd_end);
112 if (initrd_start &&
113 ((initrd_pstart > MAX_RAM_SIZE)
114 || (initrd_pend > MAX_RAM_SIZE))) {
115 panic("initrd out of addressable memory");
116 }
117
118#endif /* INITRD */
119
120 for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE;
121 idx++) {
122 rd_flag = 0;
123 if (type == CFE_MI_AVAILABLE) {
124 /*
125 * See if this block contains (any portion of) the
126 * ramdisk
127 */
128#ifdef CONFIG_BLK_DEV_INITRD
129 if (initrd_start) {
130 if ((initrd_pstart > addr) &&
131 (initrd_pstart < (addr + size))) {
132 add_memory_region(addr,
133 initrd_pstart - addr,
134 BOOT_MEM_RAM);
135 rd_flag = 1;
136 }
137 if ((initrd_pend > addr) &&
138 (initrd_pend < (addr + size))) {
139 add_memory_region(initrd_pend,
140 (addr + size) - initrd_pend,
141 BOOT_MEM_RAM);
142 rd_flag = 1;
143 }
144 }
145#endif
146 if (!rd_flag) {
147 if (addr > MAX_RAM_SIZE)
148 continue;
149 if (addr+size > MAX_RAM_SIZE)
150 size = MAX_RAM_SIZE - (addr+size) + 1;
151 /*
152 * memcpy/__copy_user prefetch, which
153 * will cause a bus error for
154 * KSEG/KUSEG addrs not backed by RAM.
155 * Hence, reserve some padding for the
156 * prefetch distance.
157 */
158 if (size > 512)
159 size -= 512;
160 add_memory_region(addr, size, BOOT_MEM_RAM);
161 }
162 board_mem_region_addrs[board_mem_region_count] = addr;
163 board_mem_region_sizes[board_mem_region_count] = size;
164 board_mem_region_count++;
165 if (board_mem_region_count ==
166 SIBYTE_MAX_MEM_REGIONS) {
167 /*
168 * Too many regions. Need to configure more
169 */
170 while(1);
171 }
172 }
173 }
174#ifdef CONFIG_BLK_DEV_INITRD
175 if (initrd_start) {
176 add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
177 BOOT_MEM_RESERVED);
178 }
179#endif
180}
181
182#ifdef CONFIG_BLK_DEV_INITRD
183static int __init initrd_setup(char *str)
184{
185 char rdarg[64];
186 int idx;
187 char *tmp, *endptr;
188 unsigned long initrd_size;
189
190 /* Make a copy of the initrd argument so we can smash it up here */
191 for (idx = 0; idx < sizeof(rdarg)-1; idx++) {
192 if (!str[idx] || (str[idx] == ' ')) break;
193 rdarg[idx] = str[idx];
194 }
195
196 rdarg[idx] = 0;
197 str = rdarg;
198
199 /*
200 *Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"
201 * e.g. initrd=3abfd@80010000. This is set up by the loader.
202 */
203 for (tmp = str; *tmp != '@'; tmp++) {
204 if (!*tmp) {
205 goto fail;
206 }
207 }
208 *tmp = 0;
209 tmp++;
210 if (!*tmp) {
211 goto fail;
212 }
213 initrd_size = simple_strtoul(str, &endptr, 16);
214 if (*endptr) {
215 *(tmp-1) = '@';
216 goto fail;
217 }
218 *(tmp-1) = '@';
219 initrd_start = simple_strtoul(tmp, &endptr, 16);
220 if (*endptr) {
221 goto fail;
222 }
223 initrd_end = initrd_start + initrd_size;
224 prom_printf("Found initrd of %lx@%lx\n", initrd_size, initrd_start);
225 return 1;
226 fail:
227 prom_printf("Bad initrd argument. Disabling initrd\n");
228 initrd_start = 0;
229 initrd_end = 0;
230 return 1;
231}
232
233#endif
234
235/*
236 * prom_init is called just after the cpu type is determined, from setup_arch()
237 */
238void __init prom_init(void)
239{
240 uint64_t cfe_ept, cfe_handle;
241 unsigned int cfe_eptseal;
242 int argc = fw_arg0;
243 char **envp = (char **) fw_arg2;
244 int *prom_vec = (int *) fw_arg3;
245#ifdef CONFIG_KGDB
246 char *arg;
247#endif
248
249 _machine_restart = cfe_linux_restart;
250 _machine_halt = cfe_linux_halt;
251 _machine_power_off = cfe_linux_halt;
252
253 /*
254 * Check if a loader was used; if NOT, the 4 arguments are
255 * what CFE gives us (handle, 0, EPT and EPTSEAL)
256 */
257 if (argc < 0) {
258 cfe_handle = (uint64_t)(long)argc;
259 cfe_ept = (long)envp;
260 cfe_eptseal = (uint32_t)(unsigned long)prom_vec;
261 } else {
262 if ((int32_t)(long)prom_vec < 0) {
263 /*
264 * Old loader; all it gives us is the handle,
265 * so use the "known" entrypoint and assume
266 * the seal.
267 */
268 cfe_handle = (uint64_t)(long)prom_vec;
269 cfe_ept = (uint64_t)((int32_t)0x9fc00500);
270 cfe_eptseal = CFE_EPTSEAL;
271 } else {
272 /*
273 * Newer loaders bundle the handle/ept/eptseal
274 * Note: prom_vec is in the loader's useg
275 * which is still alive in the TLB.
276 */
277 cfe_handle = (uint64_t)((int32_t *)prom_vec)[0];
278 cfe_ept = (uint64_t)((int32_t *)prom_vec)[2];
279 cfe_eptseal = (unsigned int)((uint32_t *)prom_vec)[3];
280 }
281 }
282 if (cfe_eptseal != CFE_EPTSEAL) {
283 /* too early for panic to do any good */
284 prom_printf("CFE's entrypoint seal doesn't match. Spinning.");
285 while (1) ;
286 }
287 cfe_init(cfe_handle, cfe_ept);
288 /*
289 * Get the handle for (at least) prom_putchar, possibly for
290 * boot console
291 */
292 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
293 if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) {
294 if (argc < 0) {
295 /*
296 * It's OK for direct boot to not provide a
297 * command line
298 */
299 strcpy(arcs_cmdline, "root=/dev/ram0 ");
300#ifdef CONFIG_SIBYTE_PTSWARM
301 strcat(arcs_cmdline, "console=ttyS0,115200 ");
302#endif
303 } else {
304 /* The loader should have set the command line */
305 /* too early for panic to do any good */
306 prom_printf("LINUX_CMDLINE not defined in cfe.");
307 while (1) ;
308 }
309 }
310
311#ifdef CONFIG_KGDB
312 if ((arg = strstr(arcs_cmdline,"kgdb=duart")) != NULL)
313 kgdb_port = (arg[10] == '0') ? 0 : 1;
314 else
315 kgdb_port = 1;
316#endif
317
318#ifdef CONFIG_BLK_DEV_INITRD
319 {
320 char *ptr;
321 /* Need to find out early whether we've got an initrd. So scan
322 the list looking now */
323 for (ptr = arcs_cmdline; *ptr; ptr++) {
324 while (*ptr == ' ') {
325 ptr++;
326 }
327 if (!strncmp(ptr, "initrd=", 7)) {
328 initrd_setup(ptr+7);
329 break;
330 } else {
331 while (*ptr && (*ptr != ' ')) {
332 ptr++;
333 }
334 }
335 }
336 }
337#endif /* CONFIG_BLK_DEV_INITRD */
338
339 /* Not sure this is needed, but it's the safe way. */
340 arcs_cmdline[CL_SIZE-1] = 0;
341
342 mips_machgroup = MACH_GROUP_SIBYTE;
343 prom_meminit();
344}
345
346unsigned long __init prom_free_prom_memory(void)
347{
348 /* Not sure what I'm supposed to do here. Nothing, I think */
349 return 0;
350}
351
352void prom_putchar(char c)
353{
354 int ret;
355
356 while ((ret = cfe_write(cfe_cons_handle, &c, 1)) == 0)
357 ;
358}
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
new file mode 100644
index 000000000000..73392190d2b1
--- /dev/null
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -0,0 +1,92 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/smp.h>
22#include <asm/processor.h>
23
24#include "cfe_api.h"
25#include "cfe_error.h"
26
27/*
28 * Use CFE to find out how many CPUs are available, setting up
29 * phys_cpu_present_map and the logical/physical mappings.
30 * XXXKW will the boot CPU ever not be physical 0?
31 *
32 * Common setup before any secondaries are started
33 */
34void __init prom_prepare_cpus(unsigned int max_cpus)
35{
36 int i, num;
37
38 cpus_clear(phys_cpu_present_map);
39 cpu_set(0, phys_cpu_present_map);
40 __cpu_number_map[0] = 0;
41 __cpu_logical_map[0] = 0;
42
43 for (i=1, num=0; i<NR_CPUS; i++) {
44 if (cfe_cpu_stop(i) == 0) {
45 cpu_set(i, phys_cpu_present_map);
46 __cpu_number_map[i] = ++num;
47 __cpu_logical_map[num] = i;
48 }
49 }
50 printk("Detected %i available secondary CPU(s)\n", num);
51}
52
53/*
54 * Setup the PC, SP, and GP of a secondary processor and start it
55 * running!
56 */
57void prom_boot_secondary(int cpu, struct task_struct *idle)
58{
59 int retval;
60
61 retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap,
62 __KSTK_TOS(idle),
63 (unsigned long)idle->thread_info, 0);
64 if (retval != 0)
65 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
66}
67
68/*
69 * Code to run on secondary just after probing the CPU
70 */
71void prom_init_secondary(void)
72{
73 extern void sb1250_smp_init(void);
74 sb1250_smp_init();
75}
76
77/*
78 * Do any tidying up before marking online and running the idle
79 * loop
80 */
81void prom_smp_finish(void)
82{
83 extern void sb1250_smp_finish(void);
84 sb1250_smp_finish();
85}
86
87/*
88 * Final cleanup after all secondaries booted
89 */
90void prom_cpus_done(void)
91{
92}
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
new file mode 100644
index 000000000000..a8af84697588
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -0,0 +1,8 @@
1obj-y := setup.o irq.o irq_handler.o time.o
2
3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_TBPROF) += bcm1250_tbprof.o
5obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
6obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
new file mode 100644
index 000000000000..7f813ae9eaff
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -0,0 +1,390 @@
1/*
2 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#define SBPROF_TB_DEBUG 0
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/slab.h>
27#include <linux/vmalloc.h>
28#include <linux/fs.h>
29#include <linux/errno.h>
30#include <linux/reboot.h>
31#include <asm/uaccess.h>
32#include <asm/io.h>
33#include <asm/sibyte/sb1250.h>
34#include <asm/sibyte/sb1250_regs.h>
35#include <asm/sibyte/sb1250_scd.h>
36#include <asm/sibyte/sb1250_int.h>
37#include <asm/sibyte/trace_prof.h>
38
39#define DEVNAME "bcm1250_tbprof"
40
41static struct sbprof_tb sbp;
42
43#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
44
45/************************************************************************
46 * Support for ZBbus sampling using the trace buffer
47 *
48 * We use the SCD performance counter interrupt, caused by a Zclk counter
49 * overflow, to trigger the start of tracing.
50 *
51 * We set the trace buffer to sample everything and freeze on
52 * overflow.
53 *
54 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
55 *
56 ************************************************************************/
57
58static u_int64_t tb_period;
59
60static void arm_tb(void)
61{
62 u_int64_t scdperfcnt;
63 u_int64_t next = (1ULL << 40) - tb_period;
64 u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
65 /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
66 trigger start of trace. XXX vary sampling period */
67 bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
68 scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
69 /* Unfortunately, in Pass 2 we must clear all counters to knock down
70 a previous interrupt request. This means that bus profiling
71 requires ALL of the SCD perf counters. */
72 bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is
73 M_SPC_CFG_ENABLE | // enable counting
74 M_SPC_CFG_CLEAR | // clear all counters
75 V_SPC_CFG_SRC1(1), // counter 1 counts cycles
76 IOADDR(A_SCD_PERF_CNT_CFG));
77 bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
78 /* Reset the trace buffer */
79 bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
80#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
81 /* XXXKW may want to expose control to the data-collector */
82 tb_options |= M_SCD_TRACE_CFG_FORCECNT;
83#endif
84 bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
85 sbp.tb_armed = 1;
86}
87
88static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
89{
90 int i;
91 DBG(printk(DEVNAME ": tb_intr\n"));
92 if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
93 /* XXX should use XKPHYS to make writes bypass L2 */
94 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
95 /* Read out trace */
96 bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
97 __asm__ __volatile__ ("sync" : : : "memory");
98 /* Loop runs backwards because bundles are read out in reverse order */
99 for (i = 256 * 6; i > 0; i -= 6) {
100 // Subscripts decrease to put bundle in the order
101 // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
102 p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi
103 p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo
104 p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi
105 p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo
106 p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi
107 p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo
108 }
109 if (!sbp.tb_enable) {
110 DBG(printk(DEVNAME ": tb_intr shutdown\n"));
111 bus_writeq(M_SCD_TRACE_CFG_RESET,
112 IOADDR(A_SCD_TRACE_CFG));
113 sbp.tb_armed = 0;
114 wake_up(&sbp.tb_sync);
115 } else {
116 arm_tb(); // knock down current interrupt and get another one later
117 }
118 } else {
119 /* No more trace buffer samples */
120 DBG(printk(DEVNAME ": tb_intr full\n"));
121 bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
122 sbp.tb_armed = 0;
123 if (!sbp.tb_enable) {
124 wake_up(&sbp.tb_sync);
125 }
126 wake_up(&sbp.tb_read);
127 }
128 return IRQ_HANDLED;
129}
130
131static irqreturn_t sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs)
132{
133 printk(DEVNAME ": unexpected pc_intr");
134 return IRQ_NONE;
135}
136
137int sbprof_zbprof_start(struct file *filp)
138{
139 u_int64_t scdperfcnt;
140
141 if (sbp.tb_enable)
142 return -EBUSY;
143
144 DBG(printk(DEVNAME ": starting\n"));
145
146 sbp.tb_enable = 1;
147 sbp.next_tb_sample = 0;
148 filp->f_pos = 0;
149
150 if (request_irq
151 (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
152 return -EBUSY;
153 }
154 /* Make sure there isn't a perf-cnt interrupt waiting */
155 scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
156 /* Disable and clear counters, override SRC_1 */
157 bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
158 M_SPC_CFG_ENABLE |
159 M_SPC_CFG_CLEAR |
160 V_SPC_CFG_SRC1(1),
161 IOADDR(A_SCD_PERF_CNT_CFG));
162
163 /* We grab this interrupt to prevent others from trying to use
164 it, even though we don't want to service the interrupts
165 (they only feed into the trace-on-interrupt mechanism) */
166 if (request_irq
167 (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
168 free_irq(K_INT_TRACE_FREEZE, &sbp);
169 return -EBUSY;
170 }
171
172 /* I need the core to mask these, but the interrupt mapper to
173 pass them through. I am exploiting my knowledge that
174 cp0_status masks out IP[5]. krw */
175 bus_writeq(K_INT_MAP_I3,
176 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
177 (K_INT_PERF_CNT << 3)));
178
179 /* Initialize address traps */
180 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
181 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
182 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
183 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
184
185 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
186 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
187 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
188 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
189
190 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
191 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
192 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
193 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
194
195 /* Initialize Trace Event 0-7 */
196 // when interrupt
197 bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
198 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
199 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
200 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
201 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
202 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
203 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
204 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
205
206 /* Initialize Trace Sequence 0-7 */
207 // Start on event 0 (interrupt)
208 bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
209 IOADDR(A_SCD_TRACE_SEQUENCE_0));
210 // dsamp when d used | asamp when a used
211 bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
212 K_SCD_TRSEQ_TRIGGER_ALL,
213 IOADDR(A_SCD_TRACE_SEQUENCE_1));
214 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
215 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
216 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
217 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
218 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
219 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
220
221 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
222 bus_writeq((1ULL << K_INT_PERF_CNT),
223 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
224
225 arm_tb();
226
227 DBG(printk(DEVNAME ": done starting\n"));
228
229 return 0;
230}
231
232int sbprof_zbprof_stop(void)
233{
234 DBG(printk(DEVNAME ": stopping\n"));
235
236 if (sbp.tb_enable) {
237 sbp.tb_enable = 0;
238 /* XXXKW there is a window here where the intr handler
239 may run, see the disable, and do the wake_up before
240 this sleep happens. */
241 if (sbp.tb_armed) {
242 DBG(printk(DEVNAME ": wait for disarm\n"));
243 interruptible_sleep_on(&sbp.tb_sync);
244 DBG(printk(DEVNAME ": disarm complete\n"));
245 }
246 free_irq(K_INT_TRACE_FREEZE, &sbp);
247 free_irq(K_INT_PERF_CNT, &sbp);
248 }
249
250 DBG(printk(DEVNAME ": done stopping\n"));
251
252 return 0;
253}
254
255static int sbprof_tb_open(struct inode *inode, struct file *filp)
256{
257 int minor;
258
259 minor = iminor(inode);
260 if (minor != 0) {
261 return -ENODEV;
262 }
263 if (sbp.open) {
264 return -EBUSY;
265 }
266
267 memset(&sbp, 0, sizeof(struct sbprof_tb));
268 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
269 if (!sbp.sbprof_tbbuf) {
270 return -ENOMEM;
271 }
272 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
273 init_waitqueue_head(&sbp.tb_sync);
274 init_waitqueue_head(&sbp.tb_read);
275 sbp.open = 1;
276
277 return 0;
278}
279
280static int sbprof_tb_release(struct inode *inode, struct file *filp)
281{
282 int minor;
283
284 minor = iminor(inode);
285 if (minor != 0 || !sbp.open) {
286 return -ENODEV;
287 }
288
289 if (sbp.tb_armed || sbp.tb_enable) {
290 sbprof_zbprof_stop();
291 }
292
293 vfree(sbp.sbprof_tbbuf);
294 sbp.open = 0;
295
296 return 0;
297}
298
299static ssize_t sbprof_tb_read(struct file *filp, char *buf,
300 size_t size, loff_t *offp)
301{
302 int cur_sample, sample_off, cur_count, sample_left;
303 char *src;
304 int count = 0;
305 char *dest = buf;
306 long cur_off = *offp;
307
308 count = 0;
309 cur_sample = cur_off / TB_SAMPLE_SIZE;
310 sample_off = cur_off % TB_SAMPLE_SIZE;
311 sample_left = TB_SAMPLE_SIZE - sample_off;
312 while (size && (cur_sample < sbp.next_tb_sample)) {
313 cur_count = size < sample_left ? size : sample_left;
314 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
315 copy_to_user(dest, src, cur_count);
316 DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
317 cur_sample, cur_count));
318 size -= cur_count;
319 sample_left -= cur_count;
320 if (!sample_left) {
321 cur_sample++;
322 sample_off = 0;
323 sample_left = TB_SAMPLE_SIZE;
324 } else {
325 sample_off += cur_count;
326 }
327 cur_off += cur_count;
328 dest += cur_count;
329 count += cur_count;
330 }
331 *offp = cur_off;
332
333 return count;
334}
335
336static int sbprof_tb_ioctl(struct inode *inode,
337 struct file *filp,
338 unsigned int command,
339 unsigned long arg)
340{
341 int error = 0;
342
343 switch (command) {
344 case SBPROF_ZBSTART:
345 error = sbprof_zbprof_start(filp);
346 break;
347 case SBPROF_ZBSTOP:
348 error = sbprof_zbprof_stop();
349 break;
350 case SBPROF_ZBWAITFULL:
351 interruptible_sleep_on(&sbp.tb_read);
352 /* XXXKW check if interrupted? */
353 return put_user(TB_FULL, (int *) arg);
354 default:
355 error = -EINVAL;
356 break;
357 }
358
359 return error;
360}
361
362static struct file_operations sbprof_tb_fops = {
363 .owner = THIS_MODULE,
364 .open = sbprof_tb_open,
365 .release = sbprof_tb_release,
366 .read = sbprof_tb_read,
367 .ioctl = sbprof_tb_ioctl,
368 .mmap = NULL,
369};
370
371static int __init sbprof_tb_init(void)
372{
373 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
374 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
375 SBPROF_TB_MAJOR);
376 return -EIO;
377 }
378 sbp.open = 0;
379 tb_period = zbbus_mhz * 10000LL;
380 printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
381 return 0;
382}
383
384static void __exit sbprof_tb_cleanup(void)
385{
386 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
387}
388
389module_init(sbprof_tb_init);
390module_exit(sbprof_tb_cleanup);
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
new file mode 100644
index 000000000000..182a16f42e2d
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -0,0 +1,259 @@
1/*
2 * Copyright (C) 2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * The Bus Watcher monitors internal bus transactions and maintains
21 * counts of transactions with error status, logging details and
22 * causing one of several interrupts. This driver provides a handler
23 * for those interrupts which aggregates the counts (to avoid
24 * saturating the 8-bit counters) and provides a presence in
25 * /proc/bus_watcher if PROC_FS is on.
26 */
27
28#include <linux/config.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/interrupt.h>
32#include <linux/sched.h>
33#include <linux/proc_fs.h>
34#include <asm/system.h>
35#include <asm/io.h>
36
37#include <asm/sibyte/sb1250.h>
38#include <asm/sibyte/sb1250_regs.h>
39#include <asm/sibyte/sb1250_int.h>
40#include <asm/sibyte/sb1250_scd.h>
41
42
43struct bw_stats_struct {
44 uint64_t status;
45 uint32_t l2_err;
46 uint32_t memio_err;
47 int status_printed;
48 unsigned long l2_cor_d;
49 unsigned long l2_bad_d;
50 unsigned long l2_cor_t;
51 unsigned long l2_bad_t;
52 unsigned long mem_cor_d;
53 unsigned long mem_bad_d;
54 unsigned long bus_error;
55} bw_stats;
56
57
58static void print_summary(uint32_t status, uint32_t l2_err,
59 uint32_t memio_err)
60{
61 printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
62 printk("\nLast recorded signature:\n");
63 printk("Request %02x from %d, answered by %d with Dcode %d\n",
64 (unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
65 (int)(G_SCD_BERR_TID(status) >> 6),
66 (int)G_SCD_BERR_RID(status),
67 (int)G_SCD_BERR_DCODE(status));
68}
69
70/*
71 * check_bus_watcher is exported for use in situations where we want
72 * to see the most recent status of the bus watcher, which might have
73 * already been destructively read out of the registers.
74 *
75 * notes: this is currently used by the cache error handler
76 * should provide locking against the interrupt handler
77 */
78void check_bus_watcher(void)
79{
80 u32 status, l2_err, memio_err;
81
82#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
83 /* Destructive read, clears register and interrupt */
84 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
85#else
86 /* Use non-destructive register */
87 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
88#endif
89 if (!(status & 0x7fffffff)) {
90 printk("Using last values reaped by bus watcher driver\n");
91 status = bw_stats.status;
92 l2_err = bw_stats.l2_err;
93 memio_err = bw_stats.memio_err;
94 } else {
95 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
96 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
97 }
98 if (status & ~(1UL << 31))
99 print_summary(status, l2_err, memio_err);
100 else
101 printk("Bus watcher indicates no error\n");
102}
103
104static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
105{
106 int len;
107
108 len = sprintf(page, "SiByte Bus Watcher statistics\n");
109 len += sprintf(page+len, "-----------------------------\n");
110 len += sprintf(page+len, "L2-d-cor %8ld\nL2-d-bad %8ld\n",
111 stats->l2_cor_d, stats->l2_bad_d);
112 len += sprintf(page+len, "L2-t-cor %8ld\nL2-t-bad %8ld\n",
113 stats->l2_cor_t, stats->l2_bad_t);
114 len += sprintf(page+len, "MC-d-cor %8ld\nMC-d-bad %8ld\n",
115 stats->mem_cor_d, stats->mem_bad_d);
116 len += sprintf(page+len, "IO-err %8ld\n", stats->bus_error);
117 len += sprintf(page+len, "\nLast recorded signature:\n");
118 len += sprintf(page+len, "Request %02x from %d, answered by %d with Dcode %d\n",
119 (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f),
120 (int)(G_SCD_BERR_TID(stats->status) >> 6),
121 (int)G_SCD_BERR_RID(stats->status),
122 (int)G_SCD_BERR_DCODE(stats->status));
123 /* XXXKW indicate multiple errors between printings, or stats
124 collection (or both)? */
125 if (stats->status & M_SCD_BERR_MULTERRS)
126 len += sprintf(page+len, "Multiple errors observed since last check.\n");
127 if (stats->status_printed) {
128 len += sprintf(page+len, "(no change since last printing)\n");
129 } else {
130 stats->status_printed = 1;
131 }
132
133 return len;
134}
135
136#ifdef CONFIG_PROC_FS
137
138/* For simplicity, I want to assume a single read is required each
139 time */
140static int bw_read_proc(char *page, char **start, off_t off,
141 int count, int *eof, void *data)
142{
143 int len;
144
145 if (off == 0) {
146 len = bw_print_buffer(page, data);
147 *start = page;
148 } else {
149 len = 0;
150 *eof = 1;
151 }
152 return len;
153}
154
155static void create_proc_decoder(struct bw_stats_struct *stats)
156{
157 struct proc_dir_entry *ent;
158
159 ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
160 bw_read_proc, stats);
161 if (!ent) {
162 printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n");
163 return;
164 }
165}
166
167#endif /* CONFIG_PROC_FS */
168
169/*
170 * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
171 *
172 * notes: possible re-entry due to multiple sources
173 * should check/indicate saturation
174 */
175static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs)
176{
177 struct bw_stats_struct *stats = data;
178 unsigned long cntr;
179#ifdef CONFIG_SIBYTE_BW_TRACE
180 int i;
181#endif
182#ifndef CONFIG_PROC_FS
183 char bw_buf[1024];
184#endif
185
186#ifdef CONFIG_SIBYTE_BW_TRACE
187 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
188 csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
189
190 for (i=0; i<256*6; i++)
191 printk("%016llx\n",
192 (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ)));
193
194 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
195 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
196#endif
197
198 /* Destructive read, clears register and interrupt */
199 stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
200 stats->status_printed = 0;
201
202 stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS));
203 stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr);
204 stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr);
205 stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr);
206 stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr);
207 csr_out32(0, IOADDR(A_BUS_L2_ERRORS));
208
209 stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
210 stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr);
211 stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr);
212 stats->bus_error += G_SCD_MEM_BUSERR(cntr);
213 csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS));
214
215#ifndef CONFIG_PROC_FS
216 bw_print_buffer(bw_buf, stats);
217 printk(bw_buf);
218#endif
219
220 return IRQ_HANDLED;
221}
222
223int __init sibyte_bus_watcher(void)
224{
225 memset(&bw_stats, 0, sizeof(struct bw_stats_struct));
226 bw_stats.status_printed = 1;
227
228 if (request_irq(K_INT_BAD_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
229 printk("Failed to register bus watcher BAD_ECC irq\n");
230 return -1;
231 }
232 if (request_irq(K_INT_COR_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
233 free_irq(K_INT_BAD_ECC, &bw_stats);
234 printk("Failed to register bus watcher COR_ECC irq\n");
235 return -1;
236 }
237 if (request_irq(K_INT_IO_BUS, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
238 free_irq(K_INT_BAD_ECC, &bw_stats);
239 free_irq(K_INT_COR_ECC, &bw_stats);
240 printk("Failed to register bus watcher IO_BUS irq\n");
241 return -1;
242 }
243
244#ifdef CONFIG_PROC_FS
245 create_proc_decoder(&bw_stats);
246#endif
247
248#ifdef CONFIG_SIBYTE_BW_TRACE
249 csr_out32((M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
250 K_SCD_TRSEQ_TRIGGER_ALL),
251 IOADDR(A_SCD_TRACE_SEQUENCE_0));
252 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
253 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
254#endif
255
256 return 0;
257}
258
259__initcall(sibyte_bus_watcher);
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
new file mode 100644
index 000000000000..2728abbc94d2
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -0,0 +1,431 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/linkage.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <linux/smp.h>
25#include <linux/mm.h>
26#include <linux/slab.h>
27#include <linux/kernel_stat.h>
28
29#include <asm/errno.h>
30#include <asm/signal.h>
31#include <asm/system.h>
32#include <asm/ptrace.h>
33#include <asm/io.h>
34
35#include <asm/sibyte/sb1250_regs.h>
36#include <asm/sibyte/sb1250_int.h>
37#include <asm/sibyte/sb1250_uart.h>
38#include <asm/sibyte/sb1250_scd.h>
39#include <asm/sibyte/sb1250.h>
40
41/*
42 * These are the routines that handle all the low level interrupt stuff.
43 * Actions handled here are: initialization of the interrupt map, requesting of
44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
45 * for interrupt lines
46 */
47
48
49#define shutdown_sb1250_irq disable_sb1250_irq
50static void end_sb1250_irq(unsigned int irq);
51static void enable_sb1250_irq(unsigned int irq);
52static void disable_sb1250_irq(unsigned int irq);
53static unsigned int startup_sb1250_irq(unsigned int irq);
54static void ack_sb1250_irq(unsigned int irq);
55#ifdef CONFIG_SMP
56static void sb1250_set_affinity(unsigned int irq, unsigned long mask);
57#endif
58
59#ifdef CONFIG_SIBYTE_HAS_LDT
60extern unsigned long ldt_eoi_space;
61#endif
62
63#ifdef CONFIG_KGDB
64static int kgdb_irq;
65
66/* Default to UART1 */
67int kgdb_port = 1;
68#ifdef CONFIG_SIBYTE_SB1250_DUART
69extern char sb1250_duart_present[];
70#endif
71#endif
72
73static struct hw_interrupt_type sb1250_irq_type = {
74 "SB1250-IMR",
75 startup_sb1250_irq,
76 shutdown_sb1250_irq,
77 enable_sb1250_irq,
78 disable_sb1250_irq,
79 ack_sb1250_irq,
80 end_sb1250_irq,
81#ifdef CONFIG_SMP
82 sb1250_set_affinity
83#else
84 NULL
85#endif
86};
87
88/* Store the CPU id (not the logical number) */
89int sb1250_irq_owner[SB1250_NR_IRQS];
90
91DEFINE_SPINLOCK(sb1250_imr_lock);
92
93void sb1250_mask_irq(int cpu, int irq)
94{
95 unsigned long flags;
96 u64 cur_ints;
97
98 spin_lock_irqsave(&sb1250_imr_lock, flags);
99 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
100 R_IMR_INTERRUPT_MASK));
101 cur_ints |= (((u64) 1) << irq);
102 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
103 R_IMR_INTERRUPT_MASK));
104 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
105}
106
107void sb1250_unmask_irq(int cpu, int irq)
108{
109 unsigned long flags;
110 u64 cur_ints;
111
112 spin_lock_irqsave(&sb1250_imr_lock, flags);
113 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
114 R_IMR_INTERRUPT_MASK));
115 cur_ints &= ~(((u64) 1) << irq);
116 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
117 R_IMR_INTERRUPT_MASK));
118 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
119}
120
121#ifdef CONFIG_SMP
122static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
123{
124 int i = 0, old_cpu, cpu, int_on;
125 u64 cur_ints;
126 irq_desc_t *desc = irq_desc + irq;
127 unsigned long flags;
128
129 while (mask) {
130 if (mask & 1) {
131 mask >>= 1;
132 break;
133 }
134 mask >>= 1;
135 i++;
136 }
137
138 if (mask) {
139 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
140 return;
141 }
142
143 /* Convert logical CPU to physical CPU */
144 cpu = cpu_logical_map(i);
145
146 /* Protect against other affinity changers and IMR manipulation */
147 spin_lock_irqsave(&desc->lock, flags);
148 spin_lock(&sb1250_imr_lock);
149
150 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
151 old_cpu = sb1250_irq_owner[irq];
152 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
153 R_IMR_INTERRUPT_MASK));
154 int_on = !(cur_ints & (((u64) 1) << irq));
155 if (int_on) {
156 /* If it was on, mask it */
157 cur_ints |= (((u64) 1) << irq);
158 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
159 R_IMR_INTERRUPT_MASK));
160 }
161 sb1250_irq_owner[irq] = cpu;
162 if (int_on) {
163 /* unmask for the new CPU */
164 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
165 R_IMR_INTERRUPT_MASK));
166 cur_ints &= ~(((u64) 1) << irq);
167 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
168 R_IMR_INTERRUPT_MASK));
169 }
170 spin_unlock(&sb1250_imr_lock);
171 spin_unlock_irqrestore(&desc->lock, flags);
172}
173#endif
174
175
176/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
177extern void sb1250_irq_handler(void);
178
179/*****************************************************************************/
180
181static unsigned int startup_sb1250_irq(unsigned int irq)
182{
183 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
184
185 return 0; /* never anything pending */
186}
187
188
189static void disable_sb1250_irq(unsigned int irq)
190{
191 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
192}
193
194static void enable_sb1250_irq(unsigned int irq)
195{
196 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
197}
198
199
200static void ack_sb1250_irq(unsigned int irq)
201{
202#ifdef CONFIG_SIBYTE_HAS_LDT
203 u64 pending;
204
205 /*
206 * If the interrupt was an HT interrupt, now is the time to
207 * clear it. NOTE: we assume the HT bridge was set up to
208 * deliver the interrupts to all CPUs (which makes affinity
209 * changing easier for us)
210 */
211 pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
212 R_IMR_LDT_INTERRUPT)));
213 pending &= ((u64)1 << (irq));
214 if (pending) {
215 int i;
216 for (i=0; i<NR_CPUS; i++) {
217 int cpu;
218#ifdef CONFIG_SMP
219 cpu = cpu_logical_map(i);
220#else
221 cpu = i;
222#endif
223 /*
224 * Clear for all CPUs so an affinity switch
225 * doesn't find an old status
226 */
227 bus_writeq(pending,
228 IOADDR(A_IMR_REGISTER(cpu,
229 R_IMR_LDT_INTERRUPT_CLR)));
230 }
231
232 /*
233 * Generate EOI. For Pass 1 parts, EOI is a nop. For
234 * Pass 2, the LDT world may be edge-triggered, but
235 * this EOI shouldn't hurt. If they are
236 * level-sensitive, the EOI is required.
237 */
238 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
239 }
240#endif
241 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
242}
243
244
245static void end_sb1250_irq(unsigned int irq)
246{
247 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
248 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
249 }
250}
251
252
253void __init init_sb1250_irqs(void)
254{
255 int i;
256
257 for (i = 0; i < NR_IRQS; i++) {
258 irq_desc[i].status = IRQ_DISABLED;
259 irq_desc[i].action = 0;
260 irq_desc[i].depth = 1;
261 if (i < SB1250_NR_IRQS) {
262 irq_desc[i].handler = &sb1250_irq_type;
263 sb1250_irq_owner[i] = 0;
264 } else {
265 irq_desc[i].handler = &no_irq_type;
266 }
267 }
268}
269
270
271static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id,
272 struct pt_regs *regs)
273{
274 return IRQ_NONE;
275}
276
277static struct irqaction sb1250_dummy_action = {
278 .handler = sb1250_dummy_handler,
279 .flags = 0,
280 .mask = CPU_MASK_NONE,
281 .name = "sb1250-private",
282 .next = NULL,
283 .dev_id = 0
284};
285
286int sb1250_steal_irq(int irq)
287{
288 irq_desc_t *desc = irq_desc + irq;
289 unsigned long flags;
290 int retval = 0;
291
292 if (irq >= SB1250_NR_IRQS)
293 return -EINVAL;
294
295 spin_lock_irqsave(&desc->lock,flags);
296 /* Don't allow sharing at all for these */
297 if (desc->action != NULL)
298 retval = -EBUSY;
299 else {
300 desc->action = &sb1250_dummy_action;
301 desc->depth = 0;
302 }
303 spin_unlock_irqrestore(&desc->lock,flags);
304 return 0;
305}
306
307/*
308 * arch_init_irq is called early in the boot sequence from init/main.c via
309 * init_IRQ. It is responsible for setting up the interrupt mapper and
310 * installing the handler that will be responsible for dispatching interrupts
311 * to the "right" place.
312 */
313/*
314 * For now, map all interrupts to IP[2]. We could save
315 * some cycles by parceling out system interrupts to different
316 * IP lines, but keep it simple for bringup. We'll also direct
317 * all interrupts to a single CPU; we should probably route
318 * PCI and LDT to one cpu and everything else to the other
319 * to balance the load a bit.
320 *
321 * On the second cpu, everything is set to IP5, which is
322 * ignored, EXCEPT the mailbox interrupt. That one is
323 * set to IP[2] so it is handled. This is needed so we
324 * can do cross-cpu function calls, as requred by SMP
325 */
326
327#define IMR_IP2_VAL K_INT_MAP_I0
328#define IMR_IP3_VAL K_INT_MAP_I1
329#define IMR_IP4_VAL K_INT_MAP_I2
330#define IMR_IP5_VAL K_INT_MAP_I3
331#define IMR_IP6_VAL K_INT_MAP_I4
332
333void __init arch_init_irq(void)
334{
335
336 unsigned int i;
337 u64 tmp;
338 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
339 STATUSF_IP1 | STATUSF_IP0;
340
341 /* Default everything to IP2 */
342 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
343 bus_writeq(IMR_IP2_VAL,
344 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
345 (i << 3)));
346 bus_writeq(IMR_IP2_VAL,
347 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
348 (i << 3)));
349 }
350
351 init_sb1250_irqs();
352
353 /*
354 * Map the high 16 bits of the mailbox registers to IP[3], for
355 * inter-cpu messages
356 */
357 /* Was I1 */
358 bus_writeq(IMR_IP3_VAL,
359 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
360 (K_INT_MBOX_0 << 3)));
361 bus_writeq(IMR_IP3_VAL,
362 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
363 (K_INT_MBOX_0 << 3)));
364
365 /* Clear the mailboxes. The firmware may leave them dirty */
366 bus_writeq(0xffffffffffffffffULL,
367 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
368 bus_writeq(0xffffffffffffffffULL,
369 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
370
371 /* Mask everything except the mailbox registers for both cpus */
372 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
373 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
374 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
375
376 sb1250_steal_irq(K_INT_MBOX_0);
377
378 /*
379 * Note that the timer interrupts are also mapped, but this is
380 * done in sb1250_time_init(). Also, the profiling driver
381 * does its own management of IP7.
382 */
383
384#ifdef CONFIG_KGDB
385 imask |= STATUSF_IP6;
386#endif
387 /* Enable necessary IPs, disable the rest */
388 change_c0_status(ST0_IM, imask);
389 set_except_vector(0, sb1250_irq_handler);
390
391#ifdef CONFIG_KGDB
392 if (kgdb_flag) {
393 kgdb_irq = K_INT_UART_0 + kgdb_port;
394
395#ifdef CONFIG_SIBYTE_SB1250_DUART
396 sb1250_duart_present[kgdb_port] = 0;
397#endif
398 /* Setup uart 1 settings, mapper */
399 bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
400
401 sb1250_steal_irq(kgdb_irq);
402 bus_writeq(IMR_IP6_VAL,
403 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
404 (kgdb_irq<<3)));
405 sb1250_unmask_irq(0, kgdb_irq);
406 }
407#endif
408}
409
410#ifdef CONFIG_KGDB
411
412#include <linux/delay.h>
413
414#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
415#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
416
417void sb1250_kgdb_interrupt(struct pt_regs *regs)
418{
419 /*
420 * Clear break-change status (allow some time for the remote
421 * host to stop the break, since we would see another
422 * interrupt on the end-of-break too)
423 */
424 kstat_this_cpu.irqs[kgdb_irq]++;
425 mdelay(500);
426 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
427 M_DUART_RX_EN | M_DUART_TX_EN);
428 set_async_breakpoint(&regs->cp0_epc);
429}
430
431#endif /* CONFIG_KGDB */
diff --git a/arch/mips/sibyte/sb1250/irq_handler.S b/arch/mips/sibyte/sb1250/irq_handler.S
new file mode 100644
index 000000000000..60edc8fb302b
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/irq_handler.S
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * sb1250_handle_int() is the routine that is actually called when an interrupt
21 * occurs. It is installed as the exception vector handler in arch_init_irq()
22 * in arch/mips/sibyte/sb1250/irq.c
23 *
24 * In the handle we figure out which interrupts need handling, and use that to
25 * call the dispatcher, which will take care of actually calling registered
26 * handlers
27 *
28 * Note that we take care of all raised interrupts in one go at the handler.
29 * This is more BSDish than the Indy code, and also, IMHO, more sane.
30 */
31#include <linux/config.h>
32
33#include <asm/addrspace.h>
34#include <asm/asm.h>
35#include <asm/mipsregs.h>
36#include <asm/regdef.h>
37#include <asm/stackframe.h>
38#include <asm/sibyte/sb1250_defs.h>
39#include <asm/sibyte/sb1250_regs.h>
40#include <asm/sibyte/sb1250_int.h>
41
42/*
43 * What a pain. We have to be really careful saving the upper 32 bits of any
44 * register across function calls if we don't want them trashed--since were
45 * running in -o32, the calling routing never saves the full 64 bits of a
46 * register across a function call. Being the interrupt handler, we're
47 * guaranteed that interrupts are disabled during this code so we don't have
48 * to worry about random interrupts blasting the high 32 bits.
49 */
50
51 .text
52 .set push
53 .set noreorder
54 .set noat
55 .set mips64
56 .align 5
57 NESTED(sb1250_irq_handler, PT_SIZE, sp)
58 SAVE_ALL
59 CLI
60
61#ifdef CONFIG_SIBYTE_SB1250_PROF
62 /* Set compare to count to silence count/compare timer interrupts */
63 mfc0 t1, CP0_COUNT
64 mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
65#endif
66 /* Read cause */
67 mfc0 s0, CP0_CAUSE
68
69#ifdef CONFIG_SIBYTE_SB1250_PROF
70 /* Cpu performance counter interrupt is routed to IP[7] */
71 andi t1, s0, CAUSEF_IP7
72 beqz t1, 0f
73 srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
74 and t1, t1, 0x4 /* mask to get just BD bit */
75 mfc0 a0, CP0_EPC
76 jal sbprof_cpu_intr
77 addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
78 j ret_from_irq
79 nop
800:
81#endif
82
83 /* Timer interrupt is routed to IP[4] */
84 andi t1, s0, CAUSEF_IP4
85 beqz t1, 1f
86 nop
87 jal sb1250_timer_interrupt
88 move a0, sp /* Pass the registers along */
89 j ret_from_irq
90 nop # delay slot
911:
92
93#ifdef CONFIG_SMP
94 /* Mailbox interrupt is routed to IP[3] */
95 andi t1, s0, CAUSEF_IP3
96 beqz t1, 2f
97 nop
98 jal sb1250_mailbox_interrupt
99 move a0, sp
100 j ret_from_irq
101 nop # delay slot
1022:
103#endif
104
105#ifdef CONFIG_KGDB
106 /* KGDB (uart 1) interrupt is routed to IP[6] */
107 andi t1, s0, CAUSEF_IP6
108 beqz t1, 1f
109 nop # delay slot
110 jal sb1250_kgdb_interrupt
111 move a0, sp
112 j ret_from_irq
113 nop # delay slot
1141:
115#endif
116
117 and t1, s0, CAUSEF_IP2
118 beqz t1, 4f
119 nop
120
121 /*
122 * Default...we've hit an IP[2] interrupt, which means we've got to
123 * check the 1250 interrupt registers to figure out what to do
124 * Need to detect which CPU we're on, now that smp_affinity is supported.
125 */
126 PTR_LA v0, CKSEG1 + A_IMR_CPU0_BASE
127#ifdef CONFIG_SMP
128 lw t1, TI_CPU($28)
129 sll t1, IMR_REGISTER_SPACING_SHIFT
130 addu v0, t1
131#endif
132 ld s0, R_IMR_INTERRUPT_STATUS_BASE(v0) /* read IP[2] status */
133
134 beqz s0, 4f /* No interrupts. Return */
135 move a1, sp
136
1373: dclz s1, s0 /* Find the next interrupt */
138 dsubu a0, zero, s1
139 daddiu a0, a0, 63
140 jal do_IRQ
141 nop
142
1434: j ret_from_irq
144 nop
145
146 .set pop
147 END(sb1250_irq_handler)
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
new file mode 100644
index 000000000000..de62ab0f55a2
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/prom.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/blkdev.h>
24#include <linux/bootmem.h>
25#include <linux/smp.h>
26#include <linux/initrd.h>
27
28#include <asm/bootinfo.h>
29#include <asm/reboot.h>
30
31#define MAX_RAM_SIZE ((CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - 1)
32
33static __init void prom_meminit(void)
34{
35#ifdef CONFIG_BLK_DEV_INITRD
36 unsigned long initrd_pstart;
37 unsigned long initrd_pend;
38
39 initrd_pstart = __pa(initrd_start);
40 initrd_pend = __pa(initrd_end);
41 if (initrd_start &&
42 ((initrd_pstart > MAX_RAM_SIZE)
43 || (initrd_pend > MAX_RAM_SIZE))) {
44 panic("initrd out of addressable memory");
45 }
46
47 add_memory_region(0, initrd_pstart,
48 BOOT_MEM_RAM);
49 add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
50 BOOT_MEM_RESERVED);
51 add_memory_region(initrd_pend,
52 (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - initrd_pend,
53 BOOT_MEM_RAM);
54#else
55 add_memory_region(0, CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024,
56 BOOT_MEM_RAM);
57#endif
58}
59
60void prom_cpu0_exit(void *unused)
61{
62 while (1) ;
63}
64
65static void prom_linux_exit(void)
66{
67#ifdef CONFIG_SMP
68 if (smp_processor_id()) {
69 smp_call_function(prom_cpu0_exit,NULL,1,1);
70 }
71#endif
72 while(1);
73}
74
75/*
76 * prom_init is called just after the cpu type is determined, from setup_arch()
77 */
78void __init prom_init(void)
79{
80 _machine_restart = (void (*)(char *))prom_linux_exit;
81 _machine_halt = prom_linux_exit;
82 _machine_power_off = prom_linux_exit;
83
84 strcpy(arcs_cmdline, "root=/dev/ram0 ");
85
86 mips_machgroup = MACH_GROUP_SIBYTE;
87 prom_meminit();
88}
89
90unsigned long __init prom_free_prom_memory(void)
91{
92 /* Not sure what I'm supposed to do here. Nothing, I think */
93 return 0;
94}
95
96void prom_putchar(char c)
97{
98}
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
new file mode 100644
index 000000000000..f8c605be96c7
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -0,0 +1,206 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/reboot.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24#include <asm/mipsregs.h>
25#include <asm/io.h>
26#include <asm/sibyte/sb1250.h>
27#include <asm/sibyte/sb1250_regs.h>
28#include <asm/sibyte/sb1250_scd.h>
29
30unsigned int sb1_pass;
31unsigned int soc_pass;
32unsigned int soc_type;
33unsigned int periph_rev;
34unsigned int zbbus_mhz;
35
36static char *soc_str;
37static char *pass_str;
38static unsigned int war_pass; /* XXXKW don't overload PASS defines? */
39
40static inline int setup_bcm1250(void);
41static inline int setup_bcm112x(void);
42
43/* Setup code likely to be common to all SiByte platforms */
44
45static inline int sys_rev_decode(void)
46{
47 int ret = 0;
48
49 war_pass = soc_pass;
50 switch (soc_type) {
51 case K_SYS_SOC_TYPE_BCM1250:
52 case K_SYS_SOC_TYPE_BCM1250_ALT:
53 case K_SYS_SOC_TYPE_BCM1250_ALT2:
54 soc_str = "BCM1250";
55 ret = setup_bcm1250();
56 break;
57 case K_SYS_SOC_TYPE_BCM1120:
58 soc_str = "BCM1120";
59 ret = setup_bcm112x();
60 break;
61 case K_SYS_SOC_TYPE_BCM1125:
62 soc_str = "BCM1125";
63 ret = setup_bcm112x();
64 break;
65 case K_SYS_SOC_TYPE_BCM1125H:
66 soc_str = "BCM1125H";
67 ret = setup_bcm112x();
68 break;
69 default:
70 prom_printf("Unknown SOC type %x\n", soc_type);
71 ret = 1;
72 break;
73 }
74 return ret;
75}
76
77static inline int setup_bcm1250(void)
78{
79 int ret = 0;
80
81 switch (soc_pass) {
82 case K_SYS_REVISION_BCM1250_PASS1:
83 periph_rev = 1;
84 pass_str = "Pass 1";
85 break;
86 case K_SYS_REVISION_BCM1250_A10:
87 periph_rev = 2;
88 pass_str = "A8/A10";
89 /* XXXKW different war_pass? */
90 war_pass = K_SYS_REVISION_BCM1250_PASS2;
91 break;
92 case K_SYS_REVISION_BCM1250_PASS2_2:
93 periph_rev = 2;
94 pass_str = "B1";
95 break;
96 case K_SYS_REVISION_BCM1250_B2:
97 periph_rev = 2;
98 pass_str = "B2";
99 war_pass = K_SYS_REVISION_BCM1250_PASS2_2;
100 break;
101 case K_SYS_REVISION_BCM1250_PASS3:
102 periph_rev = 3;
103 pass_str = "C0";
104 break;
105 case K_SYS_REVISION_BCM1250_C1:
106 periph_rev = 3;
107 pass_str = "C1";
108 break;
109 default:
110 if (soc_pass < K_SYS_REVISION_BCM1250_PASS2_2) {
111 periph_rev = 2;
112 pass_str = "A0-A6";
113 war_pass = K_SYS_REVISION_BCM1250_PASS2;
114 } else {
115 prom_printf("Unknown BCM1250 rev %x\n", soc_pass);
116 ret = 1;
117 }
118 break;
119 }
120 return ret;
121}
122
123static inline int setup_bcm112x(void)
124{
125 int ret = 0;
126
127 switch (soc_pass) {
128 case 0:
129 /* Early build didn't have revid set */
130 periph_rev = 3;
131 pass_str = "A1";
132 war_pass = K_SYS_REVISION_BCM112x_A1;
133 break;
134 case K_SYS_REVISION_BCM112x_A1:
135 periph_rev = 3;
136 pass_str = "A1";
137 break;
138 case K_SYS_REVISION_BCM112x_A2:
139 periph_rev = 3;
140 pass_str = "A2";
141 break;
142 default:
143 prom_printf("Unknown %s rev %x\n", soc_str, soc_pass);
144 ret = 1;
145 }
146 return ret;
147}
148
149void sb1250_setup(void)
150{
151 uint64_t sys_rev;
152 int plldiv;
153 int bad_config = 0;
154
155 sb1_pass = read_c0_prid() & 0xff;
156 sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION));
157 soc_type = SYS_SOC_TYPE(sys_rev);
158 soc_pass = G_SYS_REVISION(sys_rev);
159
160 if (sys_rev_decode()) {
161 prom_printf("Restart after failure to identify SiByte chip\n");
162 machine_restart(NULL);
163 }
164
165 plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG)));
166 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
167
168 prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
169 soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
170 prom_printf("Board type: %s\n", get_system_type());
171
172 switch(war_pass) {
173 case K_SYS_REVISION_BCM1250_PASS1:
174#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
175 prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
176 bad_config = 1;
177#endif
178 break;
179 case K_SYS_REVISION_BCM1250_PASS2:
180 /* Pass 2 - easiest as default for now - so many numbers */
181#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
182 prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
183 bad_config = 1;
184#endif
185#ifdef CONFIG_CPU_HAS_PREFETCH
186 prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n");
187 bad_config = 1;
188#endif
189 break;
190 case K_SYS_REVISION_BCM1250_PASS2_2:
191#ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
192 prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
193 bad_config = 1;
194#endif
195#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH)
196 prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n");
197#endif
198 break;
199 default:
200 break;
201 }
202 if (bad_config) {
203 prom_printf("Invalid configuration for this chip.\n");
204 machine_restart(NULL);
205 }
206}
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
new file mode 100644
index 000000000000..be91b3990952
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/smp.h>
23#include <linux/kernel_stat.h>
24
25#include <asm/mmu_context.h>
26#include <asm/io.h>
27#include <asm/sibyte/sb1250.h>
28#include <asm/sibyte/sb1250_regs.h>
29#include <asm/sibyte/sb1250_int.h>
30
31static void *mailbox_set_regs[] = {
32 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
33 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
34};
35
36static void *mailbox_clear_regs[] = {
37 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
38 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
39};
40
41static void *mailbox_regs[] = {
42 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
43 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
44};
45
46/*
47 * SMP init and finish on secondary CPUs
48 */
49void sb1250_smp_init(void)
50{
51 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
52 STATUSF_IP1 | STATUSF_IP0;
53
54 /* Set interrupt mask, but don't enable */
55 change_c0_status(ST0_IM, imask);
56}
57
58void sb1250_smp_finish(void)
59{
60 extern void sb1250_time_init(void);
61 sb1250_time_init();
62 local_irq_enable();
63}
64
65/*
66 * These are routines for dealing with the sb1250 smp capabilities
67 * independent of board/firmware
68 */
69
70/*
71 * Simple enough; everything is set up, so just poke the appropriate mailbox
72 * register, and we should be set
73 */
74void core_send_ipi(int cpu, unsigned int action)
75{
76 bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
77}
78
79void sb1250_mailbox_interrupt(struct pt_regs *regs)
80{
81 int cpu = smp_processor_id();
82 unsigned int action;
83
84 kstat_this_cpu.irqs[K_INT_MBOX_0]++;
85 /* Load the mailbox register to figure out what we're supposed to do */
86 action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
87
88 /* Clear the mailbox to clear the interrupt */
89 __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
90
91 /*
92 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
93 * interrupt will do the reschedule for us
94 */
95
96 if (action & SMP_CALL_FUNCTION)
97 smp_call_function_interrupt();
98}
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
new file mode 100644
index 000000000000..8b4c848c907b
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * These are routines to set up and handle interrupts from the
21 * sb1250 general purpose timer 0. We're using the timer as a
22 * system clock, so we set it up to run at 100 Hz. On every
23 * interrupt, we update our idea of what the time of day is,
24 * then call do_timer() in the architecture-independent kernel
25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.)
27 */
28#include <linux/config.h>
29#include <linux/interrupt.h>
30#include <linux/sched.h>
31#include <linux/spinlock.h>
32#include <linux/kernel_stat.h>
33
34#include <asm/irq.h>
35#include <asm/ptrace.h>
36#include <asm/addrspace.h>
37#include <asm/time.h>
38#include <asm/io.h>
39
40#include <asm/sibyte/sb1250.h>
41#include <asm/sibyte/sb1250_regs.h>
42#include <asm/sibyte/sb1250_int.h>
43#include <asm/sibyte/sb1250_scd.h>
44
45
46#define IMR_IP2_VAL K_INT_MAP_I0
47#define IMR_IP3_VAL K_INT_MAP_I1
48#define IMR_IP4_VAL K_INT_MAP_I2
49
50extern int sb1250_steal_irq(int irq);
51
52void sb1250_time_init(void)
53{
54 int cpu = smp_processor_id();
55 int irq = K_INT_TIMER_0+cpu;
56
57 /* Only have 4 general purpose timers */
58 if (cpu > 3) {
59 BUG();
60 }
61
62 if (!cpu) {
63 /* Use our own gettimeoffset() routine */
64 do_gettimeoffset = sb1250_gettimeoffset;
65 }
66
67 sb1250_mask_irq(cpu, irq);
68
69 /* Map the timer interrupt to ip[4] of this cpu */
70 bus_writeq(IMR_IP4_VAL,
71 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
72 (irq << 3)));
73
74 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
75 /* Disable the timer and set up the count */
76 bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
77#ifdef CONFIG_SIMULATION
78 bus_writeq(50000 / HZ,
79 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
80#else
81 bus_writeq(1000000/HZ,
82 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
83#endif
84
85 /* Set the timer running */
86 bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
87 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
88
89 sb1250_unmask_irq(cpu, irq);
90 sb1250_steal_irq(irq);
91 /*
92 * This interrupt is "special" in that it doesn't use the request_irq
93 * way to hook the irq line. The timer interrupt is initialized early
94 * enough to make this a major pain, and it's also firing enough to
95 * warrant a bit of special case code. sb1250_timer_interrupt is
96 * called directly from irq_handler.S when IP[4] is set during an
97 * interrupt
98 */
99}
100
101void sb1250_timer_interrupt(struct pt_regs *regs)
102{
103 extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
104 int cpu = smp_processor_id();
105 int irq = K_INT_TIMER_0 + cpu;
106
107 /* Reset the timer */
108 __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
109 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
110
111 /*
112 * CPU 0 handles the global timer interrupt job
113 */
114 if (cpu == 0) {
115 ll_timer_interrupt(irq, regs);
116 }
117
118 /*
119 * every CPU should do profiling and process accouting
120 */
121 ll_local_timer_interrupt(irq, regs);
122}
123
124/*
125 * We use our own do_gettimeoffset() instead of the generic one,
126 * because the generic one does not work for SMP case.
127 * In addition, since we use general timer 0 for system time,
128 * we can get accurate intra-jiffy offset without calibration.
129 */
130unsigned long sb1250_gettimeoffset(void)
131{
132 unsigned long count =
133 bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
134
135 return 1000000/HZ - count;
136 }
diff --git a/arch/mips/sibyte/swarm/Makefile b/arch/mips/sibyte/swarm/Makefile
new file mode 100644
index 000000000000..2d626039195c
--- /dev/null
+++ b/arch/mips/sibyte/swarm/Makefile
@@ -0,0 +1,3 @@
1lib-y = setup.o rtc_xicor1241.o rtc_m41t81.o
2
3lib-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
new file mode 100644
index 000000000000..75ce14c8eb69
--- /dev/null
+++ b/arch/mips/sibyte/swarm/dbg_io.c
@@ -0,0 +1,76 @@
1/*
2 * kgdb debug routines for SiByte boards.
3 *
4 * Copyright (C) 2001 MontaVista Software Inc.
5 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14/* -------------------- BEGINNING OF CONFIG --------------------- */
15
16#include <linux/delay.h>
17#include <asm/io.h>
18#include <asm/sibyte/sb1250.h>
19#include <asm/sibyte/sb1250_regs.h>
20#include <asm/sibyte/sb1250_uart.h>
21#include <asm/sibyte/sb1250_int.h>
22#include <asm/addrspace.h>
23
24/*
25 * We use the second serial port for kgdb traffic.
26 * 115200, 8, N, 1.
27 */
28
29#define BAUD_RATE 115200
30#define CLK_DIVISOR V_DUART_BAUD_RATE(BAUD_RATE)
31#define DATA_BITS V_DUART_BITS_PER_CHAR_8 /* or 7 */
32#define PARITY V_DUART_PARITY_MODE_NONE /* or even */
33#define STOP_BITS M_DUART_STOP_BIT_LEN_1 /* or 2 */
34
35static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
36
37/* -------------------- END OF CONFIG --------------------- */
38extern int kgdb_port;
39
40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
42
43void putDebugChar(unsigned char c);
44unsigned char getDebugChar(void);
45static void
46duart_init(int clk_divisor, int data, int parity, int stop)
47{
48 duart_out(R_DUART_MODE_REG_1, data | parity);
49 duart_out(R_DUART_MODE_REG_2, stop);
50 duart_out(R_DUART_CLK_SEL, clk_divisor);
51
52 duart_out(R_DUART_CMD, M_DUART_RX_EN | M_DUART_TX_EN); /* enable rx and tx */
53}
54
55void
56putDebugChar(unsigned char c)
57{
58 if (!duart_initialized) {
59 duart_initialized = 1;
60 duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
61 }
62 while ((duart_in(R_DUART_STATUS) & M_DUART_TX_RDY) == 0);
63 duart_out(R_DUART_TX_HOLD, c);
64}
65
66unsigned char
67getDebugChar(void)
68{
69 if (!duart_initialized) {
70 duart_initialized = 1;
71 duart_init(CLK_DIVISOR, DATA_BITS, PARITY, STOP_BITS);
72 }
73 while ((duart_in(R_DUART_STATUS) & M_DUART_RX_RDY) == 0) ;
74 return duart_in(R_DUART_RX_HOLD);
75}
76
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
new file mode 100644
index 000000000000..0e633ee8d83c
--- /dev/null
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -0,0 +1,224 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13#include <linux/bcd.h>
14#include <linux/types.h>
15#include <linux/time.h>
16
17#include <asm/time.h>
18#include <asm/addrspace.h>
19#include <asm/io.h>
20
21#include <asm/sibyte/sb1250.h>
22#include <asm/sibyte/sb1250_regs.h>
23#include <asm/sibyte/sb1250_smbus.h>
24
25
26/* M41T81 definitions */
27
28/*
29 * Register bits
30 */
31
32#define M41T81REG_SC_ST 0x80 /* stop bit */
33#define M41T81REG_HR_CB 0x40 /* century bit */
34#define M41T81REG_HR_CEB 0x80 /* century enable bit */
35#define M41T81REG_CTL_S 0x20 /* sign bit */
36#define M41T81REG_CTL_FT 0x40 /* frequency test bit */
37#define M41T81REG_CTL_OUT 0x80 /* output level */
38#define M41T81REG_WD_RB0 0x01 /* watchdog resolution bit 0 */
39#define M41T81REG_WD_RB1 0x02 /* watchdog resolution bit 1 */
40#define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
41#define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
42#define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
43#define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
44#define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
45#define M41T81REG_AMO_ABE 0x20 /* alarm in "battery back-up mode" enable bit */
46#define M41T81REG_AMO_SQWE 0x40 /* square wave enable */
47#define M41T81REG_AMO_AFE 0x80 /* alarm flag enable flag */
48#define M41T81REG_ADT_RPT5 0x40 /* alarm repeat mode bit 5 */
49#define M41T81REG_ADT_RPT4 0x80 /* alarm repeat mode bit 4 */
50#define M41T81REG_AHR_RPT3 0x80 /* alarm repeat mode bit 3 */
51#define M41T81REG_AHR_HT 0x40 /* halt update bit */
52#define M41T81REG_AMN_RPT2 0x80 /* alarm repeat mode bit 2 */
53#define M41T81REG_ASC_RPT1 0x80 /* alarm repeat mode bit 1 */
54#define M41T81REG_FLG_AF 0x40 /* alarm flag (read only) */
55#define M41T81REG_FLG_WDF 0x80 /* watchdog flag (read only) */
56#define M41T81REG_SQW_RS0 0x10 /* sqw frequency bit 0 */
57#define M41T81REG_SQW_RS1 0x20 /* sqw frequency bit 1 */
58#define M41T81REG_SQW_RS2 0x40 /* sqw frequency bit 2 */
59#define M41T81REG_SQW_RS3 0x80 /* sqw frequency bit 3 */
60
61
62/*
63 * Register numbers
64 */
65
66#define M41T81REG_TSC 0x00 /* tenths/hundredths of second */
67#define M41T81REG_SC 0x01 /* seconds */
68#define M41T81REG_MN 0x02 /* minute */
69#define M41T81REG_HR 0x03 /* hour/century */
70#define M41T81REG_DY 0x04 /* day of week */
71#define M41T81REG_DT 0x05 /* date of month */
72#define M41T81REG_MO 0x06 /* month */
73#define M41T81REG_YR 0x07 /* year */
74#define M41T81REG_CTL 0x08 /* control */
75#define M41T81REG_WD 0x09 /* watchdog */
76#define M41T81REG_AMO 0x0A /* alarm: month */
77#define M41T81REG_ADT 0x0B /* alarm: date */
78#define M41T81REG_AHR 0x0C /* alarm: hour */
79#define M41T81REG_AMN 0x0D /* alarm: minute */
80#define M41T81REG_ASC 0x0E /* alarm: second */
81#define M41T81REG_FLG 0x0F /* flags */
82#define M41T81REG_SQW 0x13 /* square wave register */
83
84#define M41T81_CCR_ADDRESS 0x68
85#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
86
87static int m41t81_read(uint8_t addr)
88{
89 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
90 ;
91
92 bus_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));
93 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR1BYTE),
94 SMB_CSR(R_SMB_START));
95
96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
97 ;
98
99 bus_writeq((V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
100 SMB_CSR(R_SMB_START));
101
102 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
103 ;
104
105 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
106 /* Clear error bit by writing a 1 */
107 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
108 return -1;
109 }
110
111 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
112}
113
114static int m41t81_write(uint8_t addr, int b)
115{
116 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
117 ;
118
119 bus_writeq((addr & 0xFF), SMB_CSR(R_SMB_CMD));
120 bus_writeq((b & 0xff), SMB_CSR(R_SMB_DATA));
121 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
122 SMB_CSR(R_SMB_START));
123
124 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
125 ;
126
127 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
128 /* Clear error bit by writing a 1 */
129 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
130 return -1;
131 }
132
133 /* read the same byte again to make sure it is written */
134 bus_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
135 SMB_CSR(R_SMB_START));
136
137 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
138 ;
139
140 return 0;
141}
142
143int m41t81_set_time(unsigned long t)
144{
145 struct rtc_time tm;
146
147 to_tm(t, &tm);
148
149 /*
150 * Note the write order matters as it ensures the correctness.
151 * When we write sec, 10th sec is clear. It is reasonable to
152 * believe we should finish writing min within a second.
153 */
154
155 tm.tm_sec = BIN2BCD(tm.tm_sec);
156 m41t81_write(M41T81REG_SC, tm.tm_sec);
157
158 tm.tm_min = BIN2BCD(tm.tm_min);
159 m41t81_write(M41T81REG_MN, tm.tm_min);
160
161 tm.tm_hour = BIN2BCD(tm.tm_hour);
162 tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);
163 m41t81_write(M41T81REG_HR, tm.tm_hour);
164
165 /* tm_wday starts from 0 to 6 */
166 if (tm.tm_wday == 0) tm.tm_wday = 7;
167 tm.tm_wday = BIN2BCD(tm.tm_wday);
168 m41t81_write(M41T81REG_DY, tm.tm_wday);
169
170 tm.tm_mday = BIN2BCD(tm.tm_mday);
171 m41t81_write(M41T81REG_DT, tm.tm_mday);
172
173 /* tm_mon starts from 0, *ick* */
174 tm.tm_mon ++;
175 tm.tm_mon = BIN2BCD(tm.tm_mon);
176 m41t81_write(M41T81REG_MO, tm.tm_mon);
177
178 /* we don't do century, everything is beyond 2000 */
179 tm.tm_year %= 100;
180 tm.tm_year = BIN2BCD(tm.tm_year);
181 m41t81_write(M41T81REG_YR, tm.tm_year);
182
183 return 0;
184}
185
186unsigned long m41t81_get_time(void)
187{
188 unsigned int year, mon, day, hour, min, sec;
189
190 /*
191 * min is valid if two reads of sec are the same.
192 */
193 for (;;) {
194 sec = m41t81_read(M41T81REG_SC);
195 min = m41t81_read(M41T81REG_MN);
196 if (sec == m41t81_read(M41T81REG_SC)) break;
197 }
198 hour = m41t81_read(M41T81REG_HR) & 0x3f;
199 day = m41t81_read(M41T81REG_DT);
200 mon = m41t81_read(M41T81REG_MO);
201 year = m41t81_read(M41T81REG_YR);
202
203 sec = BCD2BIN(sec);
204 min = BCD2BIN(min);
205 hour = BCD2BIN(hour);
206 day = BCD2BIN(day);
207 mon = BCD2BIN(mon);
208 year = BCD2BIN(year);
209
210 year += 2000;
211
212 return mktime(year, mon, day, hour, min, sec);
213}
214
215int m41t81_probe(void)
216{
217 unsigned int tmp;
218
219 /* enable chip if it is not enabled yet */
220 tmp = m41t81_read(M41T81REG_SC);
221 m41t81_write(M41T81REG_SC, tmp & 0x7f);
222
223 return (m41t81_read(M41T81REG_SC) != -1);
224}
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
new file mode 100644
index 000000000000..981d21f16e64
--- /dev/null
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -0,0 +1,203 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: jsun@mvista.com or jsun@junsun.net
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12#include <linux/bcd.h>
13#include <linux/types.h>
14#include <linux/time.h>
15
16#include <asm/time.h>
17#include <asm/addrspace.h>
18#include <asm/io.h>
19
20#include <asm/sibyte/sb1250.h>
21#include <asm/sibyte/sb1250_regs.h>
22#include <asm/sibyte/sb1250_smbus.h>
23
24
25/* Xicor 1241 definitions */
26
27/*
28 * Register bits
29 */
30
31#define X1241REG_SR_BAT 0x80 /* currently on battery power */
32#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
33#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
34#define X1241REG_SR_RTCF 0x01 /* clock failed */
35#define X1241REG_BL_BP2 0x80 /* block protect 2 */
36#define X1241REG_BL_BP1 0x40 /* block protect 1 */
37#define X1241REG_BL_BP0 0x20 /* block protect 0 */
38#define X1241REG_BL_WD1 0x10
39#define X1241REG_BL_WD0 0x08
40#define X1241REG_HR_MIL 0x80 /* military time format */
41
42/*
43 * Register numbers
44 */
45
46#define X1241REG_BL 0x10 /* block protect bits */
47#define X1241REG_INT 0x11 /* */
48#define X1241REG_SC 0x30 /* Seconds */
49#define X1241REG_MN 0x31 /* Minutes */
50#define X1241REG_HR 0x32 /* Hours */
51#define X1241REG_DT 0x33 /* Day of month */
52#define X1241REG_MO 0x34 /* Month */
53#define X1241REG_YR 0x35 /* Year */
54#define X1241REG_DW 0x36 /* Day of Week */
55#define X1241REG_Y2K 0x37 /* Year 2K */
56#define X1241REG_SR 0x3F /* Status register */
57
58#define X1241_CCR_ADDRESS 0x6F
59
60#define SMB_CSR(reg) ((u8 *) (IOADDR(A_SMB_REGISTER(1, reg))))
61
62static int xicor_read(uint8_t addr)
63{
64 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
65 ;
66
67 bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
68 bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
69 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
70 SMB_CSR(R_SMB_START));
71
72 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
73 ;
74
75 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
76 SMB_CSR(R_SMB_START));
77
78 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
79 ;
80
81 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
82 /* Clear error bit by writing a 1 */
83 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
84 return -1;
85 }
86
87 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
88}
89
90static int xicor_write(uint8_t addr, int b)
91{
92 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
93 ;
94
95 bus_writeq(addr, SMB_CSR(R_SMB_CMD));
96 bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
97 bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
98 SMB_CSR(R_SMB_START));
99
100 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
101 ;
102
103 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
104 /* Clear error bit by writing a 1 */
105 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
106 return -1;
107 } else {
108 return 0;
109 }
110}
111
112int xicor_set_time(unsigned long t)
113{
114 struct rtc_time tm;
115 int tmp;
116
117 to_tm(t, &tm);
118
119 /* unlock writes to the CCR */
120 xicor_write(X1241REG_SR, X1241REG_SR_WEL);
121 xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
122
123 /* trivial ones */
124 tm.tm_sec = BIN2BCD(tm.tm_sec);
125 xicor_write(X1241REG_SC, tm.tm_sec);
126
127 tm.tm_min = BIN2BCD(tm.tm_min);
128 xicor_write(X1241REG_MN, tm.tm_min);
129
130 tm.tm_mday = BIN2BCD(tm.tm_mday);
131 xicor_write(X1241REG_DT, tm.tm_mday);
132
133 /* tm_mon starts from 0, *ick* */
134 tm.tm_mon ++;
135 tm.tm_mon = BIN2BCD(tm.tm_mon);
136 xicor_write(X1241REG_MO, tm.tm_mon);
137
138 /* year is split */
139 tmp = tm.tm_year / 100;
140 tm.tm_year %= 100;
141 xicor_write(X1241REG_YR, tm.tm_year);
142 xicor_write(X1241REG_Y2K, tmp);
143
144 /* hour is the most tricky one */
145 tmp = xicor_read(X1241REG_HR);
146 if (tmp & X1241REG_HR_MIL) {
147 /* 24 hour format */
148 tm.tm_hour = BIN2BCD(tm.tm_hour);
149 tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f);
150 } else {
151 /* 12 hour format, with 0x2 for pm */
152 tmp = tmp & ~0x3f;
153 if (tm.tm_hour >= 12) {
154 tmp |= 0x20;
155 tm.tm_hour -= 12;
156 }
157 tm.tm_hour = BIN2BCD(tm.tm_hour);
158 tmp |= tm.tm_hour;
159 }
160 xicor_write(X1241REG_HR, tmp);
161
162 xicor_write(X1241REG_SR, 0);
163
164 return 0;
165}
166
167unsigned long xicor_get_time(void)
168{
169 unsigned int year, mon, day, hour, min, sec, y2k;
170
171 sec = xicor_read(X1241REG_SC);
172 min = xicor_read(X1241REG_MN);
173 hour = xicor_read(X1241REG_HR);
174
175 if (hour & X1241REG_HR_MIL) {
176 hour &= 0x3f;
177 } else {
178 if (hour & 0x20)
179 hour = (hour & 0xf) + 0x12;
180 }
181
182 day = xicor_read(X1241REG_DT);
183 mon = xicor_read(X1241REG_MO);
184 year = xicor_read(X1241REG_YR);
185 y2k = xicor_read(X1241REG_Y2K);
186
187 sec = BCD2BIN(sec);
188 min = BCD2BIN(min);
189 hour = BCD2BIN(hour);
190 day = BCD2BIN(day);
191 mon = BCD2BIN(mon);
192 year = BCD2BIN(year);
193 y2k = BCD2BIN(y2k);
194
195 year += (y2k * 100);
196
197 return mktime(year, mon, day, hour, min, sec);
198}
199
200int xicor_probe(void)
201{
202 return (xicor_read(X1241REG_SC) != -1);
203}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
new file mode 100644
index 000000000000..457aeb7be858
--- /dev/null
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -0,0 +1,163 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * Setup code for the SWARM board
22 */
23
24#include <linux/config.h>
25#include <linux/spinlock.h>
26#include <linux/mm.h>
27#include <linux/bootmem.h>
28#include <linux/blkdev.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/tty.h>
32#include <linux/initrd.h>
33
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/bootinfo.h>
37#include <asm/mipsregs.h>
38#include <asm/reboot.h>
39#include <asm/time.h>
40#include <asm/traps.h>
41#include <asm/sibyte/sb1250.h>
42#include <asm/sibyte/sb1250_regs.h>
43#include <asm/sibyte/sb1250_genbus.h>
44#include <asm/sibyte/board.h>
45
46extern void sb1250_setup(void);
47
48extern int xicor_probe(void);
49extern int xicor_set_time(unsigned long);
50extern unsigned long xicor_get_time(void);
51
52extern int m41t81_probe(void);
53extern int m41t81_set_time(unsigned long);
54extern unsigned long m41t81_get_time(void);
55
56const char *get_system_type(void)
57{
58 return "SiByte " SIBYTE_BOARD_NAME;
59}
60
61void __init swarm_timer_setup(struct irqaction *irq)
62{
63 /*
64 * we don't set up irqaction, because we will deliver timer
65 * interrupts through low-level (direct) meachanism.
66 */
67
68 /* We only need to setup the generic timer */
69 sb1250_time_init();
70}
71
72int swarm_be_handler(struct pt_regs *regs, int is_fixup)
73{
74 if (!is_fixup && (regs->cp0_cause & 4)) {
75 /* Data bus error - print PA */
76#ifdef CONFIG_MIPS64
77 printk("DBE physical address: %010lx\n",
78 __read_64bit_c0_register($26, 1));
79#else
80 printk("DBE physical address: %010llx\n",
81 __read_64bit_c0_split($26, 1));
82#endif
83 }
84 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
85}
86
87static int __init swarm_setup(void)
88{
89 sb1250_setup();
90
91 panic_timeout = 5; /* For debug. */
92
93 board_timer_setup = swarm_timer_setup;
94 board_be_handler = swarm_be_handler;
95
96 if (xicor_probe()) {
97 printk("swarm setup: Xicor 1241 RTC detected.\n");
98 rtc_get_time = xicor_get_time;
99 rtc_set_time = xicor_set_time;
100 }
101
102 if (m41t81_probe()) {
103 printk("swarm setup: M41T81 RTC detected.\n");
104 rtc_get_time = m41t81_get_time;
105 rtc_set_time = m41t81_set_time;
106 }
107
108 printk("This kernel optimized for "
109#ifdef CONFIG_SIMULATION
110 "simulation"
111#else
112 "board"
113#endif
114 " runs "
115#ifdef CONFIG_SIBYTE_CFE
116 "with"
117#else
118 "without"
119#endif
120 " CFE\n");
121
122#ifdef CONFIG_VT
123 screen_info = (struct screen_info) {
124 0, 0, /* orig-x, orig-y */
125 0, /* unused */
126 52, /* orig_video_page */
127 3, /* orig_video_mode */
128 80, /* orig_video_cols */
129 4626, 3, 9, /* unused, ega_bx, unused */
130 25, /* orig_video_lines */
131 0x22, /* orig_video_isVGA */
132 16 /* orig_video_points */
133 };
134 /* XXXKW for CFE, get lines/cols from environment */
135#endif
136
137 return 0;
138}
139
140early_initcall(swarm_setup);
141
142#ifdef LEDS_PHYS
143
144#ifdef CONFIG_SIBYTE_CARMEL
145/* XXXKW need to detect Monterey/LittleSur/etc */
146#undef LEDS_PHYS
147#define LEDS_PHYS MLEDS_PHYS
148#endif
149
150#define setled(index, c) \
151 ((unsigned char *)(IOADDR(LEDS_PHYS)+0x20))[(3-(index))<<3] = (c)
152void setleds(char *str)
153{
154 int i;
155 for (i = 0; i < 4; i++) {
156 if (!str[i]) {
157 setled(i, ' ');
158 } else {
159 setled(i, str[i]);
160 }
161 }
162}
163#endif
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c
new file mode 100644
index 000000000000..c1f1a9defeeb
--- /dev/null
+++ b/arch/mips/sibyte/swarm/time.c
@@ -0,0 +1,244 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * Time routines for the swarm board. We pass all the hard stuff
21 * through to the sb1250 handling code. Only thing we really keep
22 * track of here is what time of day we think it is. And we don't
23 * really even do a good job of that...
24 */
25
26
27#include <linux/bcd.h>
28#include <linux/init.h>
29#include <linux/time.h>
30#include <linux/sched.h>
31#include <linux/spinlock.h>
32#include <asm/system.h>
33#include <asm/addrspace.h>
34#include <asm/io.h>
35
36#include <asm/sibyte/sb1250.h>
37#include <asm/sibyte/sb1250_regs.h>
38#include <asm/sibyte/sb1250_smbus.h>
39
40static unsigned long long sec_bias = 0;
41static unsigned int usec_bias = 0;
42
43/* Xicor 1241 definitions */
44
45/*
46 * Register bits
47 */
48
49#define X1241REG_SR_BAT 0x80 /* currently on battery power */
50#define X1241REG_SR_RWEL 0x04 /* r/w latch is enabled, can write RTC */
51#define X1241REG_SR_WEL 0x02 /* r/w latch is unlocked, can enable r/w now */
52#define X1241REG_SR_RTCF 0x01 /* clock failed */
53#define X1241REG_BL_BP2 0x80 /* block protect 2 */
54#define X1241REG_BL_BP1 0x40 /* block protect 1 */
55#define X1241REG_BL_BP0 0x20 /* block protect 0 */
56#define X1241REG_BL_WD1 0x10
57#define X1241REG_BL_WD0 0x08
58#define X1241REG_HR_MIL 0x80 /* military time format */
59
60/*
61 * Register numbers
62 */
63
64#define X1241REG_BL 0x10 /* block protect bits */
65#define X1241REG_INT 0x11 /* */
66#define X1241REG_SC 0x30 /* Seconds */
67#define X1241REG_MN 0x31 /* Minutes */
68#define X1241REG_HR 0x32 /* Hours */
69#define X1241REG_DT 0x33 /* Day of month */
70#define X1241REG_MO 0x34 /* Month */
71#define X1241REG_YR 0x35 /* Year */
72#define X1241REG_DW 0x36 /* Day of Week */
73#define X1241REG_Y2K 0x37 /* Year 2K */
74#define X1241REG_SR 0x3F /* Status register */
75
76#define X1241_CCR_ADDRESS 0x6F
77
78#define SMB_CSR(reg) (IOADDR(A_SMB_REGISTER(1, reg)))
79
80static int xicor_read(uint8_t addr)
81{
82 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
83 ;
84
85 bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
86 bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA));
87 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE),
88 SMB_CSR(R_SMB_START));
89
90 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
91 ;
92
93 bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE),
94 SMB_CSR(R_SMB_START));
95
96 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
97 ;
98
99 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
100 /* Clear error bit by writing a 1 */
101 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
102 return -1;
103 }
104
105 return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
106}
107
108static int xicor_write(uint8_t addr, int b)
109{
110 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
111 ;
112
113 bus_writeq(addr, SMB_CSR(R_SMB_CMD));
114 bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
115 bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
116 SMB_CSR(R_SMB_START));
117
118 while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
119 ;
120
121 if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
122 /* Clear error bit by writing a 1 */
123 bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
124 return -1;
125 } else {
126 return 0;
127 }
128}
129
130/*
131 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
132 * called 500 ms after the second nowtime has started, because when
133 * nowtime is written into the registers of the CMOS clock, it will
134 * jump to the next second precisely 500 ms later. Check the Motorola
135 * MC146818A or Dallas DS12887 data sheet for details.
136 *
137 * BUG: This routine does not handle hour overflow properly; it just
138 * sets the minutes. Usually you'll only notice that after reboot!
139 */
140int set_rtc_mmss(unsigned long nowtime)
141{
142 int retval = 0;
143 int real_seconds, real_minutes, cmos_minutes;
144
145 cmos_minutes = xicor_read(X1241REG_MN);
146 cmos_minutes = BCD2BIN(cmos_minutes);
147
148 /*
149 * since we're only adjusting minutes and seconds,
150 * don't interfere with hour overflow. This avoids
151 * messing with unknown time zones but requires your
152 * RTC not to be off by more than 15 minutes
153 */
154 real_seconds = nowtime % 60;
155 real_minutes = nowtime / 60;
156 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
157 real_minutes += 30; /* correct for half hour time zone */
158 real_minutes %= 60;
159
160 /* unlock writes to the CCR */
161 xicor_write(X1241REG_SR, X1241REG_SR_WEL);
162 xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
163
164 if (abs(real_minutes - cmos_minutes) < 30) {
165 real_seconds = BIN2BCD(real_seconds);
166 real_minutes = BIN2BCD(real_minutes);
167 xicor_write(X1241REG_SC, real_seconds);
168 xicor_write(X1241REG_MN, real_minutes);
169 } else {
170 printk(KERN_WARNING
171 "set_rtc_mmss: can't update from %d to %d\n",
172 cmos_minutes, real_minutes);
173 retval = -1;
174 }
175
176 xicor_write(X1241REG_SR, 0);
177
178 printk("set_rtc_mmss: %02d:%02d\n", real_minutes, real_seconds);
179
180 return retval;
181}
182
183static unsigned long __init get_swarm_time(void)
184{
185 unsigned int year, mon, day, hour, min, sec, y2k;
186
187 sec = xicor_read(X1241REG_SC);
188 min = xicor_read(X1241REG_MN);
189 hour = xicor_read(X1241REG_HR);
190
191 if (hour & X1241REG_HR_MIL) {
192 hour &= 0x3f;
193 } else {
194 if (hour & 0x20)
195 hour = (hour & 0xf) + 0x12;
196 }
197
198 sec = BCD2BIN(sec);
199 min = BCD2BIN(min);
200 hour = BCD2BIN(hour);
201
202 day = xicor_read(X1241REG_DT);
203 mon = xicor_read(X1241REG_MO);
204 year = xicor_read(X1241REG_YR);
205 y2k = xicor_read(X1241REG_Y2K);
206
207 day = BCD2BIN(day);
208 mon = BCD2BIN(mon);
209 year = BCD2BIN(year);
210 y2k = BCD2BIN(y2k);
211
212 year += (y2k * 100);
213
214 return mktime(year, mon, day, hour, min, sec);
215}
216
217/*
218 * Bring up the timer at 100 Hz.
219 */
220void __init swarm_time_init(void)
221{
222 unsigned int flags;
223 int status;
224
225 /* Set up the scd general purpose timer 0 to cpu 0 */
226 sb1250_time_init();
227
228 /* Establish communication with the Xicor 1241 RTC */
229 /* XXXKW how do I share the SMBus with the I2C subsystem? */
230
231 bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ));
232 bus_writeq(0, SMB_CSR(R_SMB_CONTROL));
233
234 if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) {
235 printk("x1241: couldn't detect on SWARM SMBus 1\n");
236 } else {
237 if (status & X1241REG_SR_RTCF)
238 printk("x1241: battery failed -- time is probably wrong\n");
239 write_seqlock_irqsave(&xtime_lock, flags);
240 xtime.tv_sec = get_swarm_time();
241 xtime.tv_nsec = 0;
242 write_sequnlock_irqrestore(&xtime_lock, flags);
243 }
244}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 17:23:03 -0500