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authorRalf Baechle <ralf@linux-mips.org>2007-10-31 21:57:55 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-11-02 12:13:47 -0400
commit217dd11e9d0442767fa13c9c188be0b92dc93d7e (patch)
tree9557e15fbad397fcc5a707e85cf1a68132ee6c31 /arch/mips/sibyte
parentf3f9ad0edcc1b7bf154bb34fe3b3f71e5379c9f0 (diff)
[MIPS] Sibyte: Split and move clock code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte')
-rw-r--r--arch/mips/sibyte/Kconfig14
-rw-r--r--arch/mips/sibyte/bcm1480/time.c160
-rw-r--r--arch/mips/sibyte/sb1250/time.c176
3 files changed, 20 insertions, 330 deletions
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index e8fb880272bd..366b19d33f77 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -1,5 +1,7 @@
1config SIBYTE_SB1250 1config SIBYTE_SB1250
2 bool 2 bool
3 select CEVT_SB1250
4 select CSRC_SB1250
3 select HW_HAS_PCI 5 select HW_HAS_PCI
4 select IRQ_CPU 6 select IRQ_CPU
5 select SIBYTE_ENABLE_LDT_IF_PCI 7 select SIBYTE_ENABLE_LDT_IF_PCI
@@ -9,6 +11,8 @@ config SIBYTE_SB1250
9 11
10config SIBYTE_BCM1120 12config SIBYTE_BCM1120
11 bool 13 bool
14 select CEVT_SB1250
15 select CSRC_SB1250
12 select IRQ_CPU 16 select IRQ_CPU
13 select SIBYTE_BCM112X 17 select SIBYTE_BCM112X
14 select SIBYTE_HAS_ZBUS_PROFILING 18 select SIBYTE_HAS_ZBUS_PROFILING
@@ -16,6 +20,8 @@ config SIBYTE_BCM1120
16 20
17config SIBYTE_BCM1125 21config SIBYTE_BCM1125
18 bool 22 bool
23 select CEVT_SB1250
24 select CSRC_SB1250
19 select HW_HAS_PCI 25 select HW_HAS_PCI
20 select IRQ_CPU 26 select IRQ_CPU
21 select SIBYTE_BCM112X 27 select SIBYTE_BCM112X
@@ -24,6 +30,8 @@ config SIBYTE_BCM1125
24 30
25config SIBYTE_BCM1125H 31config SIBYTE_BCM1125H
26 bool 32 bool
33 select CEVT_SB1250
34 select CSRC_SB1250
27 select HW_HAS_PCI 35 select HW_HAS_PCI
28 select IRQ_CPU 36 select IRQ_CPU
29 select SIBYTE_BCM112X 37 select SIBYTE_BCM112X
@@ -33,12 +41,16 @@ config SIBYTE_BCM1125H
33 41
34config SIBYTE_BCM112X 42config SIBYTE_BCM112X
35 bool 43 bool
44 select CEVT_SB1250
45 select CSRC_SB1250
36 select IRQ_CPU 46 select IRQ_CPU
37 select SIBYTE_SB1xxx_SOC 47 select SIBYTE_SB1xxx_SOC
38 select SIBYTE_HAS_ZBUS_PROFILING 48 select SIBYTE_HAS_ZBUS_PROFILING
39 49
40config SIBYTE_BCM1x80 50config SIBYTE_BCM1x80
41 bool 51 bool
52 select CEVT_BCM1480
53 select CSRC_BCM1480
42 select HW_HAS_PCI 54 select HW_HAS_PCI
43 select IRQ_CPU 55 select IRQ_CPU
44 select SIBYTE_HAS_ZBUS_PROFILING 56 select SIBYTE_HAS_ZBUS_PROFILING
@@ -47,6 +59,8 @@ config SIBYTE_BCM1x80
47 59
48config SIBYTE_BCM1x55 60config SIBYTE_BCM1x55
49 bool 61 bool
62 select CEVT_BCM1480
63 select CSRC_BCM1480
50 select HW_HAS_PCI 64 select HW_HAS_PCI
51 select IRQ_CPU 65 select IRQ_CPU
52 select SIBYTE_SB1xxx_SOC 66 select SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 2bcaf5419ac1..1680a68952ae 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -15,164 +15,10 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18#include <linux/clockchips.h> 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/percpu.h>
21 19
22#include <asm/addrspace.h> 20extern void sb1480_clockevent_init(void);
23#include <asm/io.h> 21extern void sb1480_clocksource_init(void);
24#include <asm/time.h>
25
26#include <asm/sibyte/bcm1480_regs.h>
27#include <asm/sibyte/sb1250_regs.h>
28#include <asm/sibyte/bcm1480_int.h>
29#include <asm/sibyte/bcm1480_scd.h>
30
31#include <asm/sibyte/sb1250.h>
32
33
34#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
35#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
36#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
37
38/*
39 * The general purpose timer ticks at 1MHz independent if
40 * the rest of the system
41 */
42static void sibyte_set_mode(enum clock_event_mode mode,
43 struct clock_event_device *evt)
44{
45 unsigned int cpu = smp_processor_id();
46 void __iomem *cfg, *init;
47
48 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
49 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
50
51 switch (mode) {
52 case CLOCK_EVT_MODE_PERIODIC:
53 __raw_writeq(0, cfg);
54 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
55 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
56 cfg);
57 break;
58
59 case CLOCK_EVT_MODE_ONESHOT:
60 /* Stop the timer until we actually program a shot */
61 case CLOCK_EVT_MODE_SHUTDOWN:
62 __raw_writeq(0, cfg);
63 break;
64
65 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
66 case CLOCK_EVT_MODE_RESUME:
67 ;
68 }
69}
70
71static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
72{
73 unsigned int cpu = smp_processor_id();
74 void __iomem *cfg, *init;
75
76 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
77 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
78
79 __raw_writeq(delta - 1, init);
80 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
81
82 return 0;
83}
84
85static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
86{
87 unsigned int cpu = smp_processor_id();
88 struct clock_event_device *cd = dev_id;
89 void __iomem *cfg;
90 unsigned long tmode;
91
92 if (cd->mode == CLOCK_EVT_MODE_PERIODIC)
93 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
94 else
95 tmode = 0;
96
97 /* ACK interrupt */
98 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
99 ____raw_writeq(tmode, cfg);
100
101 cd->event_handler(cd);
102
103 return IRQ_HANDLED;
104}
105
106static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
107static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
108static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
109
110void __cpuinit sb1480_clockevent_init(void)
111{
112 unsigned int cpu = smp_processor_id();
113 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
114 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
115 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
116 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
117
118 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
119
120 sprintf(name, "bcm1480-counter-%d", cpu);
121 cd->name = name;
122 cd->features = CLOCK_EVT_FEAT_PERIODIC |
123 CLOCK_EVT_FEAT_ONESHOT;
124 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
125 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
126 cd->min_delta_ns = clockevent_delta2ns(1, cd);
127 cd->rating = 200;
128 cd->irq = irq;
129 cd->cpumask = cpumask_of_cpu(cpu);
130 cd->set_next_event = sibyte_next_event;
131 cd->set_mode = sibyte_set_mode;
132 clockevents_register_device(cd);
133
134 bcm1480_mask_irq(cpu, irq);
135
136 /*
137 * Map the timer interrupt to IP[4] of this cpu
138 */
139 __raw_writeq(IMR_IP4_VAL,
140 IOADDR(A_BCM1480_IMR_REGISTER(cpu,
141 R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
142
143 bcm1480_unmask_irq(cpu, irq);
144
145 action->handler = sibyte_counter_handler;
146 action->flags = IRQF_DISABLED | IRQF_PERCPU;
147 action->name = name;
148 action->dev_id = cd;
149 setup_irq(irq, action);
150}
151
152static cycle_t bcm1480_hpt_read(void)
153{
154 return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
155}
156
157struct clocksource bcm1480_clocksource = {
158 .name = "zbbus-cycles",
159 .rating = 200,
160 .read = bcm1480_hpt_read,
161 .mask = CLOCKSOURCE_MASK(64),
162 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
163};
164
165void __init sb1480_clocksource_init(void)
166{
167 struct clocksource *cs = &bcm1480_clocksource;
168 unsigned int plldiv;
169 unsigned long zbbus;
170
171 plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
172 zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
173 clocksource_set_clock(cs, zbbus);
174 clocksource_register(cs);
175}
176 22
177void __init plat_time_init(void) 23void __init plat_time_init(void)
178{ 24{
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 24b9c8bad62f..68337bf7a5aa 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -15,180 +15,10 @@
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */ 17 */
18#include <linux/clockchips.h> 18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/percpu.h>
21 19
22#include <asm/addrspace.h> 20extern void sb1250_clocksource_init(void);
23#include <asm/io.h> 21extern void sb1250_clockevent_init(void);
24#include <asm/time.h>
25
26#include <asm/sibyte/sb1250.h>
27#include <asm/sibyte/sb1250_regs.h>
28#include <asm/sibyte/sb1250_int.h>
29#include <asm/sibyte/sb1250_scd.h>
30
31#define IMR_IP2_VAL K_INT_MAP_I0
32#define IMR_IP3_VAL K_INT_MAP_I1
33#define IMR_IP4_VAL K_INT_MAP_I2
34
35#define SB1250_HPT_NUM 3
36#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */
37
38/*
39 * The general purpose timer ticks at 1MHz independent if
40 * the rest of the system
41 */
42static void sibyte_set_mode(enum clock_event_mode mode,
43 struct clock_event_device *evt)
44{
45 unsigned int cpu = smp_processor_id();
46 void __iomem *cfg, *init;
47
48 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
49 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
50
51 switch (mode) {
52 case CLOCK_EVT_MODE_PERIODIC:
53 __raw_writeq(0, cfg);
54 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init);
55 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
56 cfg);
57 break;
58
59 case CLOCK_EVT_MODE_ONESHOT:
60 /* Stop the timer until we actually program a shot */
61 case CLOCK_EVT_MODE_SHUTDOWN:
62 __raw_writeq(0, cfg);
63 break;
64
65 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
66 case CLOCK_EVT_MODE_RESUME:
67 ;
68 }
69}
70
71static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
72{
73 unsigned int cpu = smp_processor_id();
74 void __iomem *cfg, *init;
75
76 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
77 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
78
79 __raw_writeq(delta - 1, init);
80 __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
81
82 return 0;
83}
84
85static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
86{
87 unsigned int cpu = smp_processor_id();
88 struct clock_event_device *cd = dev_id;
89 void __iomem *cfg;
90 unsigned long tmode;
91
92 if (cd->mode == CLOCK_EVT_MODE_PERIODIC)
93 tmode = M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS;
94 else
95 tmode = 0;
96
97 /* ACK interrupt */
98 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
99 ____raw_writeq(tmode, cfg);
100
101 cd->event_handler(cd);
102
103 return IRQ_HANDLED;
104}
105
106static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
107static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
108static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
109
110void __cpuinit sb1250_clockevent_init(void)
111{
112 unsigned int cpu = smp_processor_id();
113 unsigned int irq = K_INT_TIMER_0 + cpu;
114 struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
115 struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
116 unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
117
118 /* Only have 4 general purpose timers, and we use last one as hpt */
119 BUG_ON(cpu > 2);
120
121 sprintf(name, "sb1250-counter-%d", cpu);
122 cd->name = name;
123 cd->features = CLOCK_EVT_FEAT_PERIODIC |
124 CLOCK_EVT_FEAT_ONESHOT;
125 clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
126 cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
127 cd->min_delta_ns = clockevent_delta2ns(1, cd);
128 cd->rating = 200;
129 cd->irq = irq;
130 cd->cpumask = cpumask_of_cpu(cpu);
131 cd->set_next_event = sibyte_next_event;
132 cd->set_mode = sibyte_set_mode;
133 clockevents_register_device(cd);
134
135 sb1250_mask_irq(cpu, irq);
136
137 /*
138 * Map the timer interrupt to IP[4] of this cpu
139 */
140 __raw_writeq(IMR_IP4_VAL,
141 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
142 (irq << 3)));
143
144 sb1250_unmask_irq(cpu, irq);
145
146 action->handler = sibyte_counter_handler;
147 action->flags = IRQF_DISABLED | IRQF_PERCPU;
148 action->name = name;
149 action->dev_id = cd;
150 setup_irq(irq, action);
151}
152
153/*
154 * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over
155 * again.
156 */
157static cycle_t sb1250_hpt_read(void)
158{
159 unsigned int count;
160
161 count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT))));
162
163 return SB1250_HPT_VALUE - count;
164}
165
166struct clocksource bcm1250_clocksource = {
167 .name = "MIPS",
168 .rating = 200,
169 .read = sb1250_hpt_read,
170 .mask = CLOCKSOURCE_MASK(23),
171 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
172};
173
174void __init sb1250_clocksource_init(void)
175{
176 struct clocksource *cs = &bcm1250_clocksource;
177
178 /* Setup hpt using timer #3 but do not enable irq for it */
179 __raw_writeq(0,
180 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
181 R_SCD_TIMER_CFG)));
182 __raw_writeq(SB1250_HPT_VALUE,
183 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
184 R_SCD_TIMER_INIT)));
185 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
186 IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM,
187 R_SCD_TIMER_CFG)));
188
189 clocksource_set_clock(cs, V_SCD_TIMER_FREQ);
190 clocksource_register(cs);
191}
192 22
193void __init plat_time_init(void) 23void __init plat_time_init(void)
194{ 24{
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