diff options
author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-02-22 16:51:30 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:30:44 -0400 |
commit | 65bda1a95d395c256818d1d8129487a4497b29d8 (patch) | |
tree | 57bea8a2593b17b987cbc188ecf07c341fda5dbc /arch/mips/sibyte/swarm/time.c | |
parent | 4912ba72d6e27d0f19ec062ffd00a8c0165a2f67 (diff) |
Switch SiByte drivers back to __raw_*() functions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/swarm/time.c')
-rw-r--r-- | arch/mips/sibyte/swarm/time.c | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/arch/mips/sibyte/swarm/time.c b/arch/mips/sibyte/swarm/time.c index c1f1a9defeeb..97c73c793c35 100644 --- a/arch/mips/sibyte/swarm/time.c +++ b/arch/mips/sibyte/swarm/time.c | |||
@@ -79,48 +79,48 @@ static unsigned int usec_bias = 0; | |||
79 | 79 | ||
80 | static int xicor_read(uint8_t addr) | 80 | static int xicor_read(uint8_t addr) |
81 | { | 81 | { |
82 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 82 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
83 | ; | 83 | ; |
84 | 84 | ||
85 | bus_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); | 85 | __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); |
86 | bus_writeq((addr & 0xff), SMB_CSR(R_SMB_DATA)); | 86 | __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); |
87 | bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE), | 87 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, |
88 | SMB_CSR(R_SMB_START)); | 88 | SMB_CSR(R_SMB_START)); |
89 | 89 | ||
90 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 90 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
91 | ; | 91 | ; |
92 | 92 | ||
93 | bus_writeq((V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE), | 93 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, |
94 | SMB_CSR(R_SMB_START)); | 94 | SMB_CSR(R_SMB_START)); |
95 | 95 | ||
96 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 96 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
97 | ; | 97 | ; |
98 | 98 | ||
99 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 99 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
100 | /* Clear error bit by writing a 1 */ | 100 | /* Clear error bit by writing a 1 */ |
101 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 101 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
102 | return -1; | 102 | return -1; |
103 | } | 103 | } |
104 | 104 | ||
105 | return (bus_readq(SMB_CSR(R_SMB_DATA)) & 0xff); | 105 | return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); |
106 | } | 106 | } |
107 | 107 | ||
108 | static int xicor_write(uint8_t addr, int b) | 108 | static int xicor_write(uint8_t addr, int b) |
109 | { | 109 | { |
110 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 110 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
111 | ; | 111 | ; |
112 | 112 | ||
113 | bus_writeq(addr, SMB_CSR(R_SMB_CMD)); | 113 | __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); |
114 | bus_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); | 114 | __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); |
115 | bus_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, | 115 | __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, |
116 | SMB_CSR(R_SMB_START)); | 116 | SMB_CSR(R_SMB_START)); |
117 | 117 | ||
118 | while (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) | 118 | while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) |
119 | ; | 119 | ; |
120 | 120 | ||
121 | if (bus_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { | 121 | if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { |
122 | /* Clear error bit by writing a 1 */ | 122 | /* Clear error bit by writing a 1 */ |
123 | bus_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); | 123 | __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); |
124 | return -1; | 124 | return -1; |
125 | } else { | 125 | } else { |
126 | return 0; | 126 | return 0; |
@@ -228,8 +228,8 @@ void __init swarm_time_init(void) | |||
228 | /* Establish communication with the Xicor 1241 RTC */ | 228 | /* Establish communication with the Xicor 1241 RTC */ |
229 | /* XXXKW how do I share the SMBus with the I2C subsystem? */ | 229 | /* XXXKW how do I share the SMBus with the I2C subsystem? */ |
230 | 230 | ||
231 | bus_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); | 231 | __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); |
232 | bus_writeq(0, SMB_CSR(R_SMB_CONTROL)); | 232 | __raw_writeq(0, SMB_CSR(R_SMB_CONTROL)); |
233 | 233 | ||
234 | if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { | 234 | if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { |
235 | printk("x1241: couldn't detect on SWARM SMBus 1\n"); | 235 | printk("x1241: couldn't detect on SWARM SMBus 1\n"); |