diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-19 15:01:22 -0400 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-19 15:01:22 -0400 |
commit | 0a4908e19fd016d60403fc76cf38b2d08d21e2d2 (patch) | |
tree | f8f33a474bfb9835625677c76735fb27fe0a2b75 /arch/mips/sibyte/sb1250 | |
parent | 2843483d2eb02ad104edbe8b2429fb6a39d25063 (diff) | |
parent | 6f75aaa72af19d3e4d144e13d59e71f51686b77f (diff) |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Delete totally outdated Documentation/mips/time.README
[MIPS] Kill duplicated setup_irq() for cp0 timer
[MIPS] Sibyte: Finish conversion to modern time APIs.
[MIPS] time: Helpers to compute clocksource/event shift and mult values.
[MIPS] SMTC: Build fix.
[MIPS] time: Delete dead code.
[MIPS] MIPSsim: Strip defconfig file to the bones.
Diffstat (limited to 'arch/mips/sibyte/sb1250')
-rw-r--r-- | arch/mips/sibyte/sb1250/irq.c | 36 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/smp.c | 5 | ||||
-rw-r--r-- | arch/mips/sibyte/sb1250/time.c | 104 |
3 files changed, 30 insertions, 115 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index 7659174819c6..500d17e84c09 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c | |||
@@ -400,43 +400,11 @@ static void sb1250_kgdb_interrupt(void) | |||
400 | 400 | ||
401 | #endif /* CONFIG_KGDB */ | 401 | #endif /* CONFIG_KGDB */ |
402 | 402 | ||
403 | static inline void sb1250_timer_interrupt(void) | ||
404 | { | ||
405 | int cpu = smp_processor_id(); | ||
406 | int irq = K_INT_TIMER_0 + cpu; | ||
407 | |||
408 | irq_enter(); | ||
409 | kstat_this_cpu.irqs[irq]++; | ||
410 | |||
411 | write_seqlock(&xtime_lock); | ||
412 | |||
413 | /* ACK interrupt */ | ||
414 | ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | ||
415 | IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); | ||
416 | |||
417 | /* | ||
418 | * call the generic timer interrupt handling | ||
419 | */ | ||
420 | do_timer(1); | ||
421 | |||
422 | write_sequnlock(&xtime_lock); | ||
423 | |||
424 | /* | ||
425 | * In UP mode, we call local_timer_interrupt() to do profiling | ||
426 | * and process accouting. | ||
427 | * | ||
428 | * In SMP mode, local_timer_interrupt() is invoked by appropriate | ||
429 | * low-level local timer interrupt handler. | ||
430 | */ | ||
431 | local_timer_interrupt(irq); | ||
432 | |||
433 | irq_exit(); | ||
434 | } | ||
435 | |||
436 | extern void sb1250_mailbox_interrupt(void); | 403 | extern void sb1250_mailbox_interrupt(void); |
437 | 404 | ||
438 | asmlinkage void plat_irq_dispatch(void) | 405 | asmlinkage void plat_irq_dispatch(void) |
439 | { | 406 | { |
407 | unsigned int cpu = smp_processor_id(); | ||
440 | unsigned int pending; | 408 | unsigned int pending; |
441 | 409 | ||
442 | /* | 410 | /* |
@@ -454,7 +422,7 @@ asmlinkage void plat_irq_dispatch(void) | |||
454 | if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ | 422 | if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */ |
455 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); | 423 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
456 | else if (pending & CAUSEF_IP4) | 424 | else if (pending & CAUSEF_IP4) |
457 | sb1250_timer_interrupt(); | 425 | do_IRQ(K_INT_TIMER_0 + cpu); /* sb1250_timer_interrupt() */ |
458 | 426 | ||
459 | #ifdef CONFIG_SMP | 427 | #ifdef CONFIG_SMP |
460 | else if (pending & CAUSEF_IP3) | 428 | else if (pending & CAUSEF_IP3) |
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index c38e1f34460d..aaa4f30dda79 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c | |||
@@ -57,8 +57,9 @@ void sb1250_smp_init(void) | |||
57 | 57 | ||
58 | void sb1250_smp_finish(void) | 58 | void sb1250_smp_finish(void) |
59 | { | 59 | { |
60 | extern void sb1250_time_init(void); | 60 | extern void sb1250_clockevent_init(void); |
61 | sb1250_time_init(); | 61 | |
62 | sb1250_clockevent_init(); | ||
62 | local_irq_enable(); | 63 | local_irq_enable(); |
63 | } | 64 | } |
64 | 65 | ||
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index fe11fed8e0d7..9ef54628bc9c 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c | |||
@@ -100,6 +100,7 @@ static void sibyte_set_mode(enum clock_event_mode mode, | |||
100 | break; | 100 | break; |
101 | 101 | ||
102 | case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ | 102 | case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ |
103 | case CLOCK_EVT_MODE_RESUME: | ||
103 | ; | 104 | ; |
104 | } | 105 | } |
105 | } | 106 | } |
@@ -144,79 +145,7 @@ static struct irqaction sibyte_irqaction = { | |||
144 | .name = "timer", | 145 | .name = "timer", |
145 | }; | 146 | }; |
146 | 147 | ||
147 | /* | 148 | void __cpuinit sb1250_clockevent_init(void) |
148 | * The general purpose timer ticks at 1 Mhz independent if | ||
149 | * the rest of the system | ||
150 | */ | ||
151 | static void sibyte_set_mode(enum clock_event_mode mode, | ||
152 | struct clock_event_device *evt) | ||
153 | { | ||
154 | unsigned int cpu = smp_processor_id(); | ||
155 | void __iomem *timer_cfg, *timer_init; | ||
156 | |||
157 | timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | ||
158 | timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); | ||
159 | |||
160 | switch (mode) { | ||
161 | case CLOCK_EVT_MODE_PERIODIC: | ||
162 | __raw_writeq(0, timer_cfg); | ||
163 | __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init); | ||
164 | __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, | ||
165 | timer_cfg); | ||
166 | break; | ||
167 | |||
168 | case CLOCK_EVT_MODE_ONESHOT: | ||
169 | /* Stop the timer until we actually program a shot */ | ||
170 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
171 | __raw_writeq(0, timer_cfg); | ||
172 | break; | ||
173 | |||
174 | case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ | ||
175 | ; | ||
176 | } | ||
177 | } | ||
178 | |||
179 | static int | ||
180 | sibyte_next_event(unsigned long delta, struct clock_event_device *evt) | ||
181 | { | ||
182 | unsigned int cpu = smp_processor_id(); | ||
183 | void __iomem *timer_cfg, *timer_init; | ||
184 | |||
185 | timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); | ||
186 | timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); | ||
187 | |||
188 | __raw_writeq(0, timer_cfg); | ||
189 | __raw_writeq(delta, timer_init); | ||
190 | __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg); | ||
191 | |||
192 | return 0; | ||
193 | } | ||
194 | |||
195 | struct clock_event_device sibyte_hpt_clockevent = { | ||
196 | .name = "sb1250-counter", | ||
197 | .features = CLOCK_EVT_FEAT_PERIODIC, | ||
198 | .set_mode = sibyte_set_mode, | ||
199 | .set_next_event = sibyte_next_event, | ||
200 | .shift = 32, | ||
201 | .irq = 0, | ||
202 | }; | ||
203 | |||
204 | static irqreturn_t sibyte_counter_handler(int irq, void *dev_id) | ||
205 | { | ||
206 | struct clock_event_device *cd = &sibyte_hpt_clockevent; | ||
207 | |||
208 | cd->event_handler(cd); | ||
209 | |||
210 | return IRQ_HANDLED; | ||
211 | } | ||
212 | |||
213 | static struct irqaction sibyte_irqaction = { | ||
214 | .handler = sibyte_counter_handler, | ||
215 | .flags = IRQF_DISABLED | IRQF_PERCPU, | ||
216 | .name = "timer", | ||
217 | }; | ||
218 | |||
219 | static void __init sb1250_clockevent_init(void) | ||
220 | { | 149 | { |
221 | struct clock_event_device *cd = &sibyte_hpt_clockevent; | 150 | struct clock_event_device *cd = &sibyte_hpt_clockevent; |
222 | unsigned int cpu = smp_processor_id(); | 151 | unsigned int cpu = smp_processor_id(); |
@@ -249,12 +178,6 @@ static void __init sb1250_clockevent_init(void) | |||
249 | clockevents_register_device(cd); | 178 | clockevents_register_device(cd); |
250 | } | 179 | } |
251 | 180 | ||
252 | void __init plat_time_init(void) | ||
253 | { | ||
254 | sb1250_clocksource_init(); | ||
255 | sb1250_clockevent_init(); | ||
256 | } | ||
257 | |||
258 | /* | 181 | /* |
259 | * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over | 182 | * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over |
260 | * again. | 183 | * again. |
@@ -267,3 +190,26 @@ static cycle_t sb1250_hpt_read(void) | |||
267 | 190 | ||
268 | return SB1250_HPT_VALUE - count; | 191 | return SB1250_HPT_VALUE - count; |
269 | } | 192 | } |
193 | |||
194 | struct clocksource bcm1250_clocksource = { | ||
195 | .name = "MIPS", | ||
196 | .rating = 200, | ||
197 | .read = sb1250_hpt_read, | ||
198 | .mask = CLOCKSOURCE_MASK(32), | ||
199 | .shift = 32, | ||
200 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
201 | }; | ||
202 | |||
203 | void __init sb1250_clocksource_init(void) | ||
204 | { | ||
205 | struct clocksource *cs = &bcm1250_clocksource; | ||
206 | |||
207 | clocksource_set_clock(cs, V_SCD_TIMER_FREQ); | ||
208 | clocksource_register(cs); | ||
209 | } | ||
210 | |||
211 | void __init plat_time_init(void) | ||
212 | { | ||
213 | sb1250_clocksource_init(); | ||
214 | sb1250_clockevent_init(); | ||
215 | } | ||