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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/sibyte/sb1250
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/sibyte/sb1250')
-rw-r--r--arch/mips/sibyte/sb1250/Makefile8
-rw-r--r--arch/mips/sibyte/sb1250/bcm1250_tbprof.c390
-rw-r--r--arch/mips/sibyte/sb1250/bus_watcher.c259
-rw-r--r--arch/mips/sibyte/sb1250/irq.c431
-rw-r--r--arch/mips/sibyte/sb1250/irq_handler.S147
-rw-r--r--arch/mips/sibyte/sb1250/prom.c98
-rw-r--r--arch/mips/sibyte/sb1250/setup.c206
-rw-r--r--arch/mips/sibyte/sb1250/smp.c98
-rw-r--r--arch/mips/sibyte/sb1250/time.c136
9 files changed, 1773 insertions, 0 deletions
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
new file mode 100644
index 000000000000..a8af84697588
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -0,0 +1,8 @@
1obj-y := setup.o irq.o irq_handler.o time.o
2
3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_TBPROF) += bcm1250_tbprof.o
5obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
6obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
7
8EXTRA_AFLAGS := $(CFLAGS)
diff --git a/arch/mips/sibyte/sb1250/bcm1250_tbprof.c b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
new file mode 100644
index 000000000000..7f813ae9eaff
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/bcm1250_tbprof.c
@@ -0,0 +1,390 @@
1/*
2 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#define SBPROF_TB_DEBUG 0
20
21#include <linux/module.h>
22#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/slab.h>
27#include <linux/vmalloc.h>
28#include <linux/fs.h>
29#include <linux/errno.h>
30#include <linux/reboot.h>
31#include <asm/uaccess.h>
32#include <asm/io.h>
33#include <asm/sibyte/sb1250.h>
34#include <asm/sibyte/sb1250_regs.h>
35#include <asm/sibyte/sb1250_scd.h>
36#include <asm/sibyte/sb1250_int.h>
37#include <asm/sibyte/trace_prof.h>
38
39#define DEVNAME "bcm1250_tbprof"
40
41static struct sbprof_tb sbp;
42
43#define TB_FULL (sbp.next_tb_sample == MAX_TB_SAMPLES)
44
45/************************************************************************
46 * Support for ZBbus sampling using the trace buffer
47 *
48 * We use the SCD performance counter interrupt, caused by a Zclk counter
49 * overflow, to trigger the start of tracing.
50 *
51 * We set the trace buffer to sample everything and freeze on
52 * overflow.
53 *
54 * We map the interrupt for trace_buffer_freeze to handle it on CPU 0.
55 *
56 ************************************************************************/
57
58static u_int64_t tb_period;
59
60static void arm_tb(void)
61{
62 u_int64_t scdperfcnt;
63 u_int64_t next = (1ULL << 40) - tb_period;
64 u_int64_t tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
65 /* Generate an SCD_PERFCNT interrupt in TB_PERIOD Zclks to
66 trigger start of trace. XXX vary sampling period */
67 bus_writeq(0, IOADDR(A_SCD_PERF_CNT_1));
68 scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
69 /* Unfortunately, in Pass 2 we must clear all counters to knock down
70 a previous interrupt request. This means that bus profiling
71 requires ALL of the SCD perf counters. */
72 bus_writeq((scdperfcnt & ~M_SPC_CFG_SRC1) | // keep counters 0,2,3 as is
73 M_SPC_CFG_ENABLE | // enable counting
74 M_SPC_CFG_CLEAR | // clear all counters
75 V_SPC_CFG_SRC1(1), // counter 1 counts cycles
76 IOADDR(A_SCD_PERF_CNT_CFG));
77 bus_writeq(next, IOADDR(A_SCD_PERF_CNT_1));
78 /* Reset the trace buffer */
79 bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
80#if 0 && defined(M_SCD_TRACE_CFG_FORCECNT)
81 /* XXXKW may want to expose control to the data-collector */
82 tb_options |= M_SCD_TRACE_CFG_FORCECNT;
83#endif
84 bus_writeq(tb_options, IOADDR(A_SCD_TRACE_CFG));
85 sbp.tb_armed = 1;
86}
87
88static irqreturn_t sbprof_tb_intr(int irq, void *dev_id, struct pt_regs *regs)
89{
90 int i;
91 DBG(printk(DEVNAME ": tb_intr\n"));
92 if (sbp.next_tb_sample < MAX_TB_SAMPLES) {
93 /* XXX should use XKPHYS to make writes bypass L2 */
94 u_int64_t *p = sbp.sbprof_tbbuf[sbp.next_tb_sample++];
95 /* Read out trace */
96 bus_writeq(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
97 __asm__ __volatile__ ("sync" : : : "memory");
98 /* Loop runs backwards because bundles are read out in reverse order */
99 for (i = 256 * 6; i > 0; i -= 6) {
100 // Subscripts decrease to put bundle in the order
101 // t0 lo, t0 hi, t1 lo, t1 hi, t2 lo, t2 hi
102 p[i-1] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 hi
103 p[i-2] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t2 lo
104 p[i-3] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 hi
105 p[i-4] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t1 lo
106 p[i-5] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 hi
107 p[i-6] = bus_readq(IOADDR(A_SCD_TRACE_READ)); // read t0 lo
108 }
109 if (!sbp.tb_enable) {
110 DBG(printk(DEVNAME ": tb_intr shutdown\n"));
111 bus_writeq(M_SCD_TRACE_CFG_RESET,
112 IOADDR(A_SCD_TRACE_CFG));
113 sbp.tb_armed = 0;
114 wake_up(&sbp.tb_sync);
115 } else {
116 arm_tb(); // knock down current interrupt and get another one later
117 }
118 } else {
119 /* No more trace buffer samples */
120 DBG(printk(DEVNAME ": tb_intr full\n"));
121 bus_writeq(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
122 sbp.tb_armed = 0;
123 if (!sbp.tb_enable) {
124 wake_up(&sbp.tb_sync);
125 }
126 wake_up(&sbp.tb_read);
127 }
128 return IRQ_HANDLED;
129}
130
131static irqreturn_t sbprof_pc_intr(int irq, void *dev_id, struct pt_regs *regs)
132{
133 printk(DEVNAME ": unexpected pc_intr");
134 return IRQ_NONE;
135}
136
137int sbprof_zbprof_start(struct file *filp)
138{
139 u_int64_t scdperfcnt;
140
141 if (sbp.tb_enable)
142 return -EBUSY;
143
144 DBG(printk(DEVNAME ": starting\n"));
145
146 sbp.tb_enable = 1;
147 sbp.next_tb_sample = 0;
148 filp->f_pos = 0;
149
150 if (request_irq
151 (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, DEVNAME " trace freeze", &sbp)) {
152 return -EBUSY;
153 }
154 /* Make sure there isn't a perf-cnt interrupt waiting */
155 scdperfcnt = bus_readq(IOADDR(A_SCD_PERF_CNT_CFG));
156 /* Disable and clear counters, override SRC_1 */
157 bus_writeq((scdperfcnt & ~(M_SPC_CFG_SRC1 | M_SPC_CFG_ENABLE)) |
158 M_SPC_CFG_ENABLE |
159 M_SPC_CFG_CLEAR |
160 V_SPC_CFG_SRC1(1),
161 IOADDR(A_SCD_PERF_CNT_CFG));
162
163 /* We grab this interrupt to prevent others from trying to use
164 it, even though we don't want to service the interrupts
165 (they only feed into the trace-on-interrupt mechanism) */
166 if (request_irq
167 (K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
168 free_irq(K_INT_TRACE_FREEZE, &sbp);
169 return -EBUSY;
170 }
171
172 /* I need the core to mask these, but the interrupt mapper to
173 pass them through. I am exploiting my knowledge that
174 cp0_status masks out IP[5]. krw */
175 bus_writeq(K_INT_MAP_I3,
176 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
177 (K_INT_PERF_CNT << 3)));
178
179 /* Initialize address traps */
180 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_0));
181 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_1));
182 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_2));
183 bus_writeq(0, IOADDR(A_ADDR_TRAP_UP_3));
184
185 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_0));
186 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_1));
187 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_2));
188 bus_writeq(0, IOADDR(A_ADDR_TRAP_DOWN_3));
189
190 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_0));
191 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_1));
192 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_2));
193 bus_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
194
195 /* Initialize Trace Event 0-7 */
196 // when interrupt
197 bus_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
198 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
199 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
200 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_3));
201 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_4));
202 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_5));
203 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_6));
204 bus_writeq(0, IOADDR(A_SCD_TRACE_EVENT_7));
205
206 /* Initialize Trace Sequence 0-7 */
207 // Start on event 0 (interrupt)
208 bus_writeq(V_SCD_TRSEQ_FUNC_START | 0x0fff,
209 IOADDR(A_SCD_TRACE_SEQUENCE_0));
210 // dsamp when d used | asamp when a used
211 bus_writeq(M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
212 K_SCD_TRSEQ_TRIGGER_ALL,
213 IOADDR(A_SCD_TRACE_SEQUENCE_1));
214 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_2));
215 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_3));
216 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_4));
217 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_5));
218 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_6));
219 bus_writeq(0, IOADDR(A_SCD_TRACE_SEQUENCE_7));
220
221 /* Now indicate the PERF_CNT interrupt as a trace-relevant interrupt */
222 bus_writeq((1ULL << K_INT_PERF_CNT),
223 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_TRACE)));
224
225 arm_tb();
226
227 DBG(printk(DEVNAME ": done starting\n"));
228
229 return 0;
230}
231
232int sbprof_zbprof_stop(void)
233{
234 DBG(printk(DEVNAME ": stopping\n"));
235
236 if (sbp.tb_enable) {
237 sbp.tb_enable = 0;
238 /* XXXKW there is a window here where the intr handler
239 may run, see the disable, and do the wake_up before
240 this sleep happens. */
241 if (sbp.tb_armed) {
242 DBG(printk(DEVNAME ": wait for disarm\n"));
243 interruptible_sleep_on(&sbp.tb_sync);
244 DBG(printk(DEVNAME ": disarm complete\n"));
245 }
246 free_irq(K_INT_TRACE_FREEZE, &sbp);
247 free_irq(K_INT_PERF_CNT, &sbp);
248 }
249
250 DBG(printk(DEVNAME ": done stopping\n"));
251
252 return 0;
253}
254
255static int sbprof_tb_open(struct inode *inode, struct file *filp)
256{
257 int minor;
258
259 minor = iminor(inode);
260 if (minor != 0) {
261 return -ENODEV;
262 }
263 if (sbp.open) {
264 return -EBUSY;
265 }
266
267 memset(&sbp, 0, sizeof(struct sbprof_tb));
268 sbp.sbprof_tbbuf = vmalloc(MAX_TBSAMPLE_BYTES);
269 if (!sbp.sbprof_tbbuf) {
270 return -ENOMEM;
271 }
272 memset(sbp.sbprof_tbbuf, 0, MAX_TBSAMPLE_BYTES);
273 init_waitqueue_head(&sbp.tb_sync);
274 init_waitqueue_head(&sbp.tb_read);
275 sbp.open = 1;
276
277 return 0;
278}
279
280static int sbprof_tb_release(struct inode *inode, struct file *filp)
281{
282 int minor;
283
284 minor = iminor(inode);
285 if (minor != 0 || !sbp.open) {
286 return -ENODEV;
287 }
288
289 if (sbp.tb_armed || sbp.tb_enable) {
290 sbprof_zbprof_stop();
291 }
292
293 vfree(sbp.sbprof_tbbuf);
294 sbp.open = 0;
295
296 return 0;
297}
298
299static ssize_t sbprof_tb_read(struct file *filp, char *buf,
300 size_t size, loff_t *offp)
301{
302 int cur_sample, sample_off, cur_count, sample_left;
303 char *src;
304 int count = 0;
305 char *dest = buf;
306 long cur_off = *offp;
307
308 count = 0;
309 cur_sample = cur_off / TB_SAMPLE_SIZE;
310 sample_off = cur_off % TB_SAMPLE_SIZE;
311 sample_left = TB_SAMPLE_SIZE - sample_off;
312 while (size && (cur_sample < sbp.next_tb_sample)) {
313 cur_count = size < sample_left ? size : sample_left;
314 src = (char *)(((long)sbp.sbprof_tbbuf[cur_sample])+sample_off);
315 copy_to_user(dest, src, cur_count);
316 DBG(printk(DEVNAME ": read from sample %d, %d bytes\n",
317 cur_sample, cur_count));
318 size -= cur_count;
319 sample_left -= cur_count;
320 if (!sample_left) {
321 cur_sample++;
322 sample_off = 0;
323 sample_left = TB_SAMPLE_SIZE;
324 } else {
325 sample_off += cur_count;
326 }
327 cur_off += cur_count;
328 dest += cur_count;
329 count += cur_count;
330 }
331 *offp = cur_off;
332
333 return count;
334}
335
336static int sbprof_tb_ioctl(struct inode *inode,
337 struct file *filp,
338 unsigned int command,
339 unsigned long arg)
340{
341 int error = 0;
342
343 switch (command) {
344 case SBPROF_ZBSTART:
345 error = sbprof_zbprof_start(filp);
346 break;
347 case SBPROF_ZBSTOP:
348 error = sbprof_zbprof_stop();
349 break;
350 case SBPROF_ZBWAITFULL:
351 interruptible_sleep_on(&sbp.tb_read);
352 /* XXXKW check if interrupted? */
353 return put_user(TB_FULL, (int *) arg);
354 default:
355 error = -EINVAL;
356 break;
357 }
358
359 return error;
360}
361
362static struct file_operations sbprof_tb_fops = {
363 .owner = THIS_MODULE,
364 .open = sbprof_tb_open,
365 .release = sbprof_tb_release,
366 .read = sbprof_tb_read,
367 .ioctl = sbprof_tb_ioctl,
368 .mmap = NULL,
369};
370
371static int __init sbprof_tb_init(void)
372{
373 if (register_chrdev(SBPROF_TB_MAJOR, DEVNAME, &sbprof_tb_fops)) {
374 printk(KERN_WARNING DEVNAME ": initialization failed (dev %d)\n",
375 SBPROF_TB_MAJOR);
376 return -EIO;
377 }
378 sbp.open = 0;
379 tb_period = zbbus_mhz * 10000LL;
380 printk(KERN_INFO DEVNAME ": initialized - tb_period = %lld\n", tb_period);
381 return 0;
382}
383
384static void __exit sbprof_tb_cleanup(void)
385{
386 unregister_chrdev(SBPROF_TB_MAJOR, DEVNAME);
387}
388
389module_init(sbprof_tb_init);
390module_exit(sbprof_tb_cleanup);
diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
new file mode 100644
index 000000000000..182a16f42e2d
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -0,0 +1,259 @@
1/*
2 * Copyright (C) 2002,2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * The Bus Watcher monitors internal bus transactions and maintains
21 * counts of transactions with error status, logging details and
22 * causing one of several interrupts. This driver provides a handler
23 * for those interrupts which aggregates the counts (to avoid
24 * saturating the 8-bit counters) and provides a presence in
25 * /proc/bus_watcher if PROC_FS is on.
26 */
27
28#include <linux/config.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/interrupt.h>
32#include <linux/sched.h>
33#include <linux/proc_fs.h>
34#include <asm/system.h>
35#include <asm/io.h>
36
37#include <asm/sibyte/sb1250.h>
38#include <asm/sibyte/sb1250_regs.h>
39#include <asm/sibyte/sb1250_int.h>
40#include <asm/sibyte/sb1250_scd.h>
41
42
43struct bw_stats_struct {
44 uint64_t status;
45 uint32_t l2_err;
46 uint32_t memio_err;
47 int status_printed;
48 unsigned long l2_cor_d;
49 unsigned long l2_bad_d;
50 unsigned long l2_cor_t;
51 unsigned long l2_bad_t;
52 unsigned long mem_cor_d;
53 unsigned long mem_bad_d;
54 unsigned long bus_error;
55} bw_stats;
56
57
58static void print_summary(uint32_t status, uint32_t l2_err,
59 uint32_t memio_err)
60{
61 printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
62 printk("\nLast recorded signature:\n");
63 printk("Request %02x from %d, answered by %d with Dcode %d\n",
64 (unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
65 (int)(G_SCD_BERR_TID(status) >> 6),
66 (int)G_SCD_BERR_RID(status),
67 (int)G_SCD_BERR_DCODE(status));
68}
69
70/*
71 * check_bus_watcher is exported for use in situations where we want
72 * to see the most recent status of the bus watcher, which might have
73 * already been destructively read out of the registers.
74 *
75 * notes: this is currently used by the cache error handler
76 * should provide locking against the interrupt handler
77 */
78void check_bus_watcher(void)
79{
80 u32 status, l2_err, memio_err;
81
82#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
83 /* Destructive read, clears register and interrupt */
84 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
85#else
86 /* Use non-destructive register */
87 status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));
88#endif
89 if (!(status & 0x7fffffff)) {
90 printk("Using last values reaped by bus watcher driver\n");
91 status = bw_stats.status;
92 l2_err = bw_stats.l2_err;
93 memio_err = bw_stats.memio_err;
94 } else {
95 l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS));
96 memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
97 }
98 if (status & ~(1UL << 31))
99 print_summary(status, l2_err, memio_err);
100 else
101 printk("Bus watcher indicates no error\n");
102}
103
104static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
105{
106 int len;
107
108 len = sprintf(page, "SiByte Bus Watcher statistics\n");
109 len += sprintf(page+len, "-----------------------------\n");
110 len += sprintf(page+len, "L2-d-cor %8ld\nL2-d-bad %8ld\n",
111 stats->l2_cor_d, stats->l2_bad_d);
112 len += sprintf(page+len, "L2-t-cor %8ld\nL2-t-bad %8ld\n",
113 stats->l2_cor_t, stats->l2_bad_t);
114 len += sprintf(page+len, "MC-d-cor %8ld\nMC-d-bad %8ld\n",
115 stats->mem_cor_d, stats->mem_bad_d);
116 len += sprintf(page+len, "IO-err %8ld\n", stats->bus_error);
117 len += sprintf(page+len, "\nLast recorded signature:\n");
118 len += sprintf(page+len, "Request %02x from %d, answered by %d with Dcode %d\n",
119 (unsigned int)(G_SCD_BERR_TID(stats->status) & 0x3f),
120 (int)(G_SCD_BERR_TID(stats->status) >> 6),
121 (int)G_SCD_BERR_RID(stats->status),
122 (int)G_SCD_BERR_DCODE(stats->status));
123 /* XXXKW indicate multiple errors between printings, or stats
124 collection (or both)? */
125 if (stats->status & M_SCD_BERR_MULTERRS)
126 len += sprintf(page+len, "Multiple errors observed since last check.\n");
127 if (stats->status_printed) {
128 len += sprintf(page+len, "(no change since last printing)\n");
129 } else {
130 stats->status_printed = 1;
131 }
132
133 return len;
134}
135
136#ifdef CONFIG_PROC_FS
137
138/* For simplicity, I want to assume a single read is required each
139 time */
140static int bw_read_proc(char *page, char **start, off_t off,
141 int count, int *eof, void *data)
142{
143 int len;
144
145 if (off == 0) {
146 len = bw_print_buffer(page, data);
147 *start = page;
148 } else {
149 len = 0;
150 *eof = 1;
151 }
152 return len;
153}
154
155static void create_proc_decoder(struct bw_stats_struct *stats)
156{
157 struct proc_dir_entry *ent;
158
159 ent = create_proc_read_entry("bus_watcher", S_IWUSR | S_IRUGO, NULL,
160 bw_read_proc, stats);
161 if (!ent) {
162 printk(KERN_INFO "Unable to initialize bus_watcher /proc entry\n");
163 return;
164 }
165}
166
167#endif /* CONFIG_PROC_FS */
168
169/*
170 * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
171 *
172 * notes: possible re-entry due to multiple sources
173 * should check/indicate saturation
174 */
175static irqreturn_t sibyte_bw_int(int irq, void *data, struct pt_regs *regs)
176{
177 struct bw_stats_struct *stats = data;
178 unsigned long cntr;
179#ifdef CONFIG_SIBYTE_BW_TRACE
180 int i;
181#endif
182#ifndef CONFIG_PROC_FS
183 char bw_buf[1024];
184#endif
185
186#ifdef CONFIG_SIBYTE_BW_TRACE
187 csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG));
188 csr_out32(M_SCD_TRACE_CFG_START_READ, IOADDR(A_SCD_TRACE_CFG));
189
190 for (i=0; i<256*6; i++)
191 printk("%016llx\n",
192 (unsigned long long)bus_readq(IOADDR(A_SCD_TRACE_READ)));
193
194 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
195 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
196#endif
197
198 /* Destructive read, clears register and interrupt */
199 stats->status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));
200 stats->status_printed = 0;
201
202 stats->l2_err = cntr = csr_in32(IOADDR(A_BUS_L2_ERRORS));
203 stats->l2_cor_d += G_SCD_L2ECC_CORR_D(cntr);
204 stats->l2_bad_d += G_SCD_L2ECC_BAD_D(cntr);
205 stats->l2_cor_t += G_SCD_L2ECC_CORR_T(cntr);
206 stats->l2_bad_t += G_SCD_L2ECC_BAD_T(cntr);
207 csr_out32(0, IOADDR(A_BUS_L2_ERRORS));
208
209 stats->memio_err = cntr = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS));
210 stats->mem_cor_d += G_SCD_MEM_ECC_CORR(cntr);
211 stats->mem_bad_d += G_SCD_MEM_ECC_BAD(cntr);
212 stats->bus_error += G_SCD_MEM_BUSERR(cntr);
213 csr_out32(0, IOADDR(A_BUS_MEM_IO_ERRORS));
214
215#ifndef CONFIG_PROC_FS
216 bw_print_buffer(bw_buf, stats);
217 printk(bw_buf);
218#endif
219
220 return IRQ_HANDLED;
221}
222
223int __init sibyte_bus_watcher(void)
224{
225 memset(&bw_stats, 0, sizeof(struct bw_stats_struct));
226 bw_stats.status_printed = 1;
227
228 if (request_irq(K_INT_BAD_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
229 printk("Failed to register bus watcher BAD_ECC irq\n");
230 return -1;
231 }
232 if (request_irq(K_INT_COR_ECC, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
233 free_irq(K_INT_BAD_ECC, &bw_stats);
234 printk("Failed to register bus watcher COR_ECC irq\n");
235 return -1;
236 }
237 if (request_irq(K_INT_IO_BUS, sibyte_bw_int, 0, "Bus watcher", &bw_stats)) {
238 free_irq(K_INT_BAD_ECC, &bw_stats);
239 free_irq(K_INT_COR_ECC, &bw_stats);
240 printk("Failed to register bus watcher IO_BUS irq\n");
241 return -1;
242 }
243
244#ifdef CONFIG_PROC_FS
245 create_proc_decoder(&bw_stats);
246#endif
247
248#ifdef CONFIG_SIBYTE_BW_TRACE
249 csr_out32((M_SCD_TRSEQ_ASAMPLE | M_SCD_TRSEQ_DSAMPLE |
250 K_SCD_TRSEQ_TRIGGER_ALL),
251 IOADDR(A_SCD_TRACE_SEQUENCE_0));
252 csr_out32(M_SCD_TRACE_CFG_RESET, IOADDR(A_SCD_TRACE_CFG));
253 csr_out32(M_SCD_TRACE_CFG_START, IOADDR(A_SCD_TRACE_CFG));
254#endif
255
256 return 0;
257}
258
259__initcall(sibyte_bus_watcher);
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
new file mode 100644
index 000000000000..2728abbc94d2
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -0,0 +1,431 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/linkage.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <linux/smp.h>
25#include <linux/mm.h>
26#include <linux/slab.h>
27#include <linux/kernel_stat.h>
28
29#include <asm/errno.h>
30#include <asm/signal.h>
31#include <asm/system.h>
32#include <asm/ptrace.h>
33#include <asm/io.h>
34
35#include <asm/sibyte/sb1250_regs.h>
36#include <asm/sibyte/sb1250_int.h>
37#include <asm/sibyte/sb1250_uart.h>
38#include <asm/sibyte/sb1250_scd.h>
39#include <asm/sibyte/sb1250.h>
40
41/*
42 * These are the routines that handle all the low level interrupt stuff.
43 * Actions handled here are: initialization of the interrupt map, requesting of
44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
45 * for interrupt lines
46 */
47
48
49#define shutdown_sb1250_irq disable_sb1250_irq
50static void end_sb1250_irq(unsigned int irq);
51static void enable_sb1250_irq(unsigned int irq);
52static void disable_sb1250_irq(unsigned int irq);
53static unsigned int startup_sb1250_irq(unsigned int irq);
54static void ack_sb1250_irq(unsigned int irq);
55#ifdef CONFIG_SMP
56static void sb1250_set_affinity(unsigned int irq, unsigned long mask);
57#endif
58
59#ifdef CONFIG_SIBYTE_HAS_LDT
60extern unsigned long ldt_eoi_space;
61#endif
62
63#ifdef CONFIG_KGDB
64static int kgdb_irq;
65
66/* Default to UART1 */
67int kgdb_port = 1;
68#ifdef CONFIG_SIBYTE_SB1250_DUART
69extern char sb1250_duart_present[];
70#endif
71#endif
72
73static struct hw_interrupt_type sb1250_irq_type = {
74 "SB1250-IMR",
75 startup_sb1250_irq,
76 shutdown_sb1250_irq,
77 enable_sb1250_irq,
78 disable_sb1250_irq,
79 ack_sb1250_irq,
80 end_sb1250_irq,
81#ifdef CONFIG_SMP
82 sb1250_set_affinity
83#else
84 NULL
85#endif
86};
87
88/* Store the CPU id (not the logical number) */
89int sb1250_irq_owner[SB1250_NR_IRQS];
90
91DEFINE_SPINLOCK(sb1250_imr_lock);
92
93void sb1250_mask_irq(int cpu, int irq)
94{
95 unsigned long flags;
96 u64 cur_ints;
97
98 spin_lock_irqsave(&sb1250_imr_lock, flags);
99 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
100 R_IMR_INTERRUPT_MASK));
101 cur_ints |= (((u64) 1) << irq);
102 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
103 R_IMR_INTERRUPT_MASK));
104 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
105}
106
107void sb1250_unmask_irq(int cpu, int irq)
108{
109 unsigned long flags;
110 u64 cur_ints;
111
112 spin_lock_irqsave(&sb1250_imr_lock, flags);
113 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
114 R_IMR_INTERRUPT_MASK));
115 cur_ints &= ~(((u64) 1) << irq);
116 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
117 R_IMR_INTERRUPT_MASK));
118 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
119}
120
121#ifdef CONFIG_SMP
122static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
123{
124 int i = 0, old_cpu, cpu, int_on;
125 u64 cur_ints;
126 irq_desc_t *desc = irq_desc + irq;
127 unsigned long flags;
128
129 while (mask) {
130 if (mask & 1) {
131 mask >>= 1;
132 break;
133 }
134 mask >>= 1;
135 i++;
136 }
137
138 if (mask) {
139 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
140 return;
141 }
142
143 /* Convert logical CPU to physical CPU */
144 cpu = cpu_logical_map(i);
145
146 /* Protect against other affinity changers and IMR manipulation */
147 spin_lock_irqsave(&desc->lock, flags);
148 spin_lock(&sb1250_imr_lock);
149
150 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
151 old_cpu = sb1250_irq_owner[irq];
152 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
153 R_IMR_INTERRUPT_MASK));
154 int_on = !(cur_ints & (((u64) 1) << irq));
155 if (int_on) {
156 /* If it was on, mask it */
157 cur_ints |= (((u64) 1) << irq);
158 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
159 R_IMR_INTERRUPT_MASK));
160 }
161 sb1250_irq_owner[irq] = cpu;
162 if (int_on) {
163 /* unmask for the new CPU */
164 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) +
165 R_IMR_INTERRUPT_MASK));
166 cur_ints &= ~(((u64) 1) << irq);
167 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
168 R_IMR_INTERRUPT_MASK));
169 }
170 spin_unlock(&sb1250_imr_lock);
171 spin_unlock_irqrestore(&desc->lock, flags);
172}
173#endif
174
175
176/* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
177extern void sb1250_irq_handler(void);
178
179/*****************************************************************************/
180
181static unsigned int startup_sb1250_irq(unsigned int irq)
182{
183 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
184
185 return 0; /* never anything pending */
186}
187
188
189static void disable_sb1250_irq(unsigned int irq)
190{
191 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
192}
193
194static void enable_sb1250_irq(unsigned int irq)
195{
196 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
197}
198
199
200static void ack_sb1250_irq(unsigned int irq)
201{
202#ifdef CONFIG_SIBYTE_HAS_LDT
203 u64 pending;
204
205 /*
206 * If the interrupt was an HT interrupt, now is the time to
207 * clear it. NOTE: we assume the HT bridge was set up to
208 * deliver the interrupts to all CPUs (which makes affinity
209 * changing easier for us)
210 */
211 pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
212 R_IMR_LDT_INTERRUPT)));
213 pending &= ((u64)1 << (irq));
214 if (pending) {
215 int i;
216 for (i=0; i<NR_CPUS; i++) {
217 int cpu;
218#ifdef CONFIG_SMP
219 cpu = cpu_logical_map(i);
220#else
221 cpu = i;
222#endif
223 /*
224 * Clear for all CPUs so an affinity switch
225 * doesn't find an old status
226 */
227 bus_writeq(pending,
228 IOADDR(A_IMR_REGISTER(cpu,
229 R_IMR_LDT_INTERRUPT_CLR)));
230 }
231
232 /*
233 * Generate EOI. For Pass 1 parts, EOI is a nop. For
234 * Pass 2, the LDT world may be edge-triggered, but
235 * this EOI shouldn't hurt. If they are
236 * level-sensitive, the EOI is required.
237 */
238 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
239 }
240#endif
241 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
242}
243
244
245static void end_sb1250_irq(unsigned int irq)
246{
247 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
248 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
249 }
250}
251
252
253void __init init_sb1250_irqs(void)
254{
255 int i;
256
257 for (i = 0; i < NR_IRQS; i++) {
258 irq_desc[i].status = IRQ_DISABLED;
259 irq_desc[i].action = 0;
260 irq_desc[i].depth = 1;
261 if (i < SB1250_NR_IRQS) {
262 irq_desc[i].handler = &sb1250_irq_type;
263 sb1250_irq_owner[i] = 0;
264 } else {
265 irq_desc[i].handler = &no_irq_type;
266 }
267 }
268}
269
270
271static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id,
272 struct pt_regs *regs)
273{
274 return IRQ_NONE;
275}
276
277static struct irqaction sb1250_dummy_action = {
278 .handler = sb1250_dummy_handler,
279 .flags = 0,
280 .mask = CPU_MASK_NONE,
281 .name = "sb1250-private",
282 .next = NULL,
283 .dev_id = 0
284};
285
286int sb1250_steal_irq(int irq)
287{
288 irq_desc_t *desc = irq_desc + irq;
289 unsigned long flags;
290 int retval = 0;
291
292 if (irq >= SB1250_NR_IRQS)
293 return -EINVAL;
294
295 spin_lock_irqsave(&desc->lock,flags);
296 /* Don't allow sharing at all for these */
297 if (desc->action != NULL)
298 retval = -EBUSY;
299 else {
300 desc->action = &sb1250_dummy_action;
301 desc->depth = 0;
302 }
303 spin_unlock_irqrestore(&desc->lock,flags);
304 return 0;
305}
306
307/*
308 * arch_init_irq is called early in the boot sequence from init/main.c via
309 * init_IRQ. It is responsible for setting up the interrupt mapper and
310 * installing the handler that will be responsible for dispatching interrupts
311 * to the "right" place.
312 */
313/*
314 * For now, map all interrupts to IP[2]. We could save
315 * some cycles by parceling out system interrupts to different
316 * IP lines, but keep it simple for bringup. We'll also direct
317 * all interrupts to a single CPU; we should probably route
318 * PCI and LDT to one cpu and everything else to the other
319 * to balance the load a bit.
320 *
321 * On the second cpu, everything is set to IP5, which is
322 * ignored, EXCEPT the mailbox interrupt. That one is
323 * set to IP[2] so it is handled. This is needed so we
324 * can do cross-cpu function calls, as requred by SMP
325 */
326
327#define IMR_IP2_VAL K_INT_MAP_I0
328#define IMR_IP3_VAL K_INT_MAP_I1
329#define IMR_IP4_VAL K_INT_MAP_I2
330#define IMR_IP5_VAL K_INT_MAP_I3
331#define IMR_IP6_VAL K_INT_MAP_I4
332
333void __init arch_init_irq(void)
334{
335
336 unsigned int i;
337 u64 tmp;
338 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
339 STATUSF_IP1 | STATUSF_IP0;
340
341 /* Default everything to IP2 */
342 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
343 bus_writeq(IMR_IP2_VAL,
344 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
345 (i << 3)));
346 bus_writeq(IMR_IP2_VAL,
347 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
348 (i << 3)));
349 }
350
351 init_sb1250_irqs();
352
353 /*
354 * Map the high 16 bits of the mailbox registers to IP[3], for
355 * inter-cpu messages
356 */
357 /* Was I1 */
358 bus_writeq(IMR_IP3_VAL,
359 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
360 (K_INT_MBOX_0 << 3)));
361 bus_writeq(IMR_IP3_VAL,
362 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
363 (K_INT_MBOX_0 << 3)));
364
365 /* Clear the mailboxes. The firmware may leave them dirty */
366 bus_writeq(0xffffffffffffffffULL,
367 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
368 bus_writeq(0xffffffffffffffffULL,
369 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
370
371 /* Mask everything except the mailbox registers for both cpus */
372 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
373 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
374 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
375
376 sb1250_steal_irq(K_INT_MBOX_0);
377
378 /*
379 * Note that the timer interrupts are also mapped, but this is
380 * done in sb1250_time_init(). Also, the profiling driver
381 * does its own management of IP7.
382 */
383
384#ifdef CONFIG_KGDB
385 imask |= STATUSF_IP6;
386#endif
387 /* Enable necessary IPs, disable the rest */
388 change_c0_status(ST0_IM, imask);
389 set_except_vector(0, sb1250_irq_handler);
390
391#ifdef CONFIG_KGDB
392 if (kgdb_flag) {
393 kgdb_irq = K_INT_UART_0 + kgdb_port;
394
395#ifdef CONFIG_SIBYTE_SB1250_DUART
396 sb1250_duart_present[kgdb_port] = 0;
397#endif
398 /* Setup uart 1 settings, mapper */
399 bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
400
401 sb1250_steal_irq(kgdb_irq);
402 bus_writeq(IMR_IP6_VAL,
403 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
404 (kgdb_irq<<3)));
405 sb1250_unmask_irq(0, kgdb_irq);
406 }
407#endif
408}
409
410#ifdef CONFIG_KGDB
411
412#include <linux/delay.h>
413
414#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
415#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
416
417void sb1250_kgdb_interrupt(struct pt_regs *regs)
418{
419 /*
420 * Clear break-change status (allow some time for the remote
421 * host to stop the break, since we would see another
422 * interrupt on the end-of-break too)
423 */
424 kstat_this_cpu.irqs[kgdb_irq]++;
425 mdelay(500);
426 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
427 M_DUART_RX_EN | M_DUART_TX_EN);
428 set_async_breakpoint(&regs->cp0_epc);
429}
430
431#endif /* CONFIG_KGDB */
diff --git a/arch/mips/sibyte/sb1250/irq_handler.S b/arch/mips/sibyte/sb1250/irq_handler.S
new file mode 100644
index 000000000000..60edc8fb302b
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/irq_handler.S
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * sb1250_handle_int() is the routine that is actually called when an interrupt
21 * occurs. It is installed as the exception vector handler in arch_init_irq()
22 * in arch/mips/sibyte/sb1250/irq.c
23 *
24 * In the handle we figure out which interrupts need handling, and use that to
25 * call the dispatcher, which will take care of actually calling registered
26 * handlers
27 *
28 * Note that we take care of all raised interrupts in one go at the handler.
29 * This is more BSDish than the Indy code, and also, IMHO, more sane.
30 */
31#include <linux/config.h>
32
33#include <asm/addrspace.h>
34#include <asm/asm.h>
35#include <asm/mipsregs.h>
36#include <asm/regdef.h>
37#include <asm/stackframe.h>
38#include <asm/sibyte/sb1250_defs.h>
39#include <asm/sibyte/sb1250_regs.h>
40#include <asm/sibyte/sb1250_int.h>
41
42/*
43 * What a pain. We have to be really careful saving the upper 32 bits of any
44 * register across function calls if we don't want them trashed--since were
45 * running in -o32, the calling routing never saves the full 64 bits of a
46 * register across a function call. Being the interrupt handler, we're
47 * guaranteed that interrupts are disabled during this code so we don't have
48 * to worry about random interrupts blasting the high 32 bits.
49 */
50
51 .text
52 .set push
53 .set noreorder
54 .set noat
55 .set mips64
56 .align 5
57 NESTED(sb1250_irq_handler, PT_SIZE, sp)
58 SAVE_ALL
59 CLI
60
61#ifdef CONFIG_SIBYTE_SB1250_PROF
62 /* Set compare to count to silence count/compare timer interrupts */
63 mfc0 t1, CP0_COUNT
64 mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
65#endif
66 /* Read cause */
67 mfc0 s0, CP0_CAUSE
68
69#ifdef CONFIG_SIBYTE_SB1250_PROF
70 /* Cpu performance counter interrupt is routed to IP[7] */
71 andi t1, s0, CAUSEF_IP7
72 beqz t1, 0f
73 srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
74 and t1, t1, 0x4 /* mask to get just BD bit */
75 mfc0 a0, CP0_EPC
76 jal sbprof_cpu_intr
77 addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
78 j ret_from_irq
79 nop
800:
81#endif
82
83 /* Timer interrupt is routed to IP[4] */
84 andi t1, s0, CAUSEF_IP4
85 beqz t1, 1f
86 nop
87 jal sb1250_timer_interrupt
88 move a0, sp /* Pass the registers along */
89 j ret_from_irq
90 nop # delay slot
911:
92
93#ifdef CONFIG_SMP
94 /* Mailbox interrupt is routed to IP[3] */
95 andi t1, s0, CAUSEF_IP3
96 beqz t1, 2f
97 nop
98 jal sb1250_mailbox_interrupt
99 move a0, sp
100 j ret_from_irq
101 nop # delay slot
1022:
103#endif
104
105#ifdef CONFIG_KGDB
106 /* KGDB (uart 1) interrupt is routed to IP[6] */
107 andi t1, s0, CAUSEF_IP6
108 beqz t1, 1f
109 nop # delay slot
110 jal sb1250_kgdb_interrupt
111 move a0, sp
112 j ret_from_irq
113 nop # delay slot
1141:
115#endif
116
117 and t1, s0, CAUSEF_IP2
118 beqz t1, 4f
119 nop
120
121 /*
122 * Default...we've hit an IP[2] interrupt, which means we've got to
123 * check the 1250 interrupt registers to figure out what to do
124 * Need to detect which CPU we're on, now that smp_affinity is supported.
125 */
126 PTR_LA v0, CKSEG1 + A_IMR_CPU0_BASE
127#ifdef CONFIG_SMP
128 lw t1, TI_CPU($28)
129 sll t1, IMR_REGISTER_SPACING_SHIFT
130 addu v0, t1
131#endif
132 ld s0, R_IMR_INTERRUPT_STATUS_BASE(v0) /* read IP[2] status */
133
134 beqz s0, 4f /* No interrupts. Return */
135 move a1, sp
136
1373: dclz s1, s0 /* Find the next interrupt */
138 dsubu a0, zero, s1
139 daddiu a0, a0, 63
140 jal do_IRQ
141 nop
142
1434: j ret_from_irq
144 nop
145
146 .set pop
147 END(sb1250_irq_handler)
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
new file mode 100644
index 000000000000..de62ab0f55a2
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/prom.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/mm.h>
23#include <linux/blkdev.h>
24#include <linux/bootmem.h>
25#include <linux/smp.h>
26#include <linux/initrd.h>
27
28#include <asm/bootinfo.h>
29#include <asm/reboot.h>
30
31#define MAX_RAM_SIZE ((CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - 1)
32
33static __init void prom_meminit(void)
34{
35#ifdef CONFIG_BLK_DEV_INITRD
36 unsigned long initrd_pstart;
37 unsigned long initrd_pend;
38
39 initrd_pstart = __pa(initrd_start);
40 initrd_pend = __pa(initrd_end);
41 if (initrd_start &&
42 ((initrd_pstart > MAX_RAM_SIZE)
43 || (initrd_pend > MAX_RAM_SIZE))) {
44 panic("initrd out of addressable memory");
45 }
46
47 add_memory_region(0, initrd_pstart,
48 BOOT_MEM_RAM);
49 add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
50 BOOT_MEM_RESERVED);
51 add_memory_region(initrd_pend,
52 (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - initrd_pend,
53 BOOT_MEM_RAM);
54#else
55 add_memory_region(0, CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024,
56 BOOT_MEM_RAM);
57#endif
58}
59
60void prom_cpu0_exit(void *unused)
61{
62 while (1) ;
63}
64
65static void prom_linux_exit(void)
66{
67#ifdef CONFIG_SMP
68 if (smp_processor_id()) {
69 smp_call_function(prom_cpu0_exit,NULL,1,1);
70 }
71#endif
72 while(1);
73}
74
75/*
76 * prom_init is called just after the cpu type is determined, from setup_arch()
77 */
78void __init prom_init(void)
79{
80 _machine_restart = (void (*)(char *))prom_linux_exit;
81 _machine_halt = prom_linux_exit;
82 _machine_power_off = prom_linux_exit;
83
84 strcpy(arcs_cmdline, "root=/dev/ram0 ");
85
86 mips_machgroup = MACH_GROUP_SIBYTE;
87 prom_meminit();
88}
89
90unsigned long __init prom_free_prom_memory(void)
91{
92 /* Not sure what I'm supposed to do here. Nothing, I think */
93 return 0;
94}
95
96void prom_putchar(char c)
97{
98}
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
new file mode 100644
index 000000000000..f8c605be96c7
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -0,0 +1,206 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/reboot.h>
21#include <linux/string.h>
22
23#include <asm/bootinfo.h>
24#include <asm/mipsregs.h>
25#include <asm/io.h>
26#include <asm/sibyte/sb1250.h>
27#include <asm/sibyte/sb1250_regs.h>
28#include <asm/sibyte/sb1250_scd.h>
29
30unsigned int sb1_pass;
31unsigned int soc_pass;
32unsigned int soc_type;
33unsigned int periph_rev;
34unsigned int zbbus_mhz;
35
36static char *soc_str;
37static char *pass_str;
38static unsigned int war_pass; /* XXXKW don't overload PASS defines? */
39
40static inline int setup_bcm1250(void);
41static inline int setup_bcm112x(void);
42
43/* Setup code likely to be common to all SiByte platforms */
44
45static inline int sys_rev_decode(void)
46{
47 int ret = 0;
48
49 war_pass = soc_pass;
50 switch (soc_type) {
51 case K_SYS_SOC_TYPE_BCM1250:
52 case K_SYS_SOC_TYPE_BCM1250_ALT:
53 case K_SYS_SOC_TYPE_BCM1250_ALT2:
54 soc_str = "BCM1250";
55 ret = setup_bcm1250();
56 break;
57 case K_SYS_SOC_TYPE_BCM1120:
58 soc_str = "BCM1120";
59 ret = setup_bcm112x();
60 break;
61 case K_SYS_SOC_TYPE_BCM1125:
62 soc_str = "BCM1125";
63 ret = setup_bcm112x();
64 break;
65 case K_SYS_SOC_TYPE_BCM1125H:
66 soc_str = "BCM1125H";
67 ret = setup_bcm112x();
68 break;
69 default:
70 prom_printf("Unknown SOC type %x\n", soc_type);
71 ret = 1;
72 break;
73 }
74 return ret;
75}
76
77static inline int setup_bcm1250(void)
78{
79 int ret = 0;
80
81 switch (soc_pass) {
82 case K_SYS_REVISION_BCM1250_PASS1:
83 periph_rev = 1;
84 pass_str = "Pass 1";
85 break;
86 case K_SYS_REVISION_BCM1250_A10:
87 periph_rev = 2;
88 pass_str = "A8/A10";
89 /* XXXKW different war_pass? */
90 war_pass = K_SYS_REVISION_BCM1250_PASS2;
91 break;
92 case K_SYS_REVISION_BCM1250_PASS2_2:
93 periph_rev = 2;
94 pass_str = "B1";
95 break;
96 case K_SYS_REVISION_BCM1250_B2:
97 periph_rev = 2;
98 pass_str = "B2";
99 war_pass = K_SYS_REVISION_BCM1250_PASS2_2;
100 break;
101 case K_SYS_REVISION_BCM1250_PASS3:
102 periph_rev = 3;
103 pass_str = "C0";
104 break;
105 case K_SYS_REVISION_BCM1250_C1:
106 periph_rev = 3;
107 pass_str = "C1";
108 break;
109 default:
110 if (soc_pass < K_SYS_REVISION_BCM1250_PASS2_2) {
111 periph_rev = 2;
112 pass_str = "A0-A6";
113 war_pass = K_SYS_REVISION_BCM1250_PASS2;
114 } else {
115 prom_printf("Unknown BCM1250 rev %x\n", soc_pass);
116 ret = 1;
117 }
118 break;
119 }
120 return ret;
121}
122
123static inline int setup_bcm112x(void)
124{
125 int ret = 0;
126
127 switch (soc_pass) {
128 case 0:
129 /* Early build didn't have revid set */
130 periph_rev = 3;
131 pass_str = "A1";
132 war_pass = K_SYS_REVISION_BCM112x_A1;
133 break;
134 case K_SYS_REVISION_BCM112x_A1:
135 periph_rev = 3;
136 pass_str = "A1";
137 break;
138 case K_SYS_REVISION_BCM112x_A2:
139 periph_rev = 3;
140 pass_str = "A2";
141 break;
142 default:
143 prom_printf("Unknown %s rev %x\n", soc_str, soc_pass);
144 ret = 1;
145 }
146 return ret;
147}
148
149void sb1250_setup(void)
150{
151 uint64_t sys_rev;
152 int plldiv;
153 int bad_config = 0;
154
155 sb1_pass = read_c0_prid() & 0xff;
156 sys_rev = bus_readq(IOADDR(A_SCD_SYSTEM_REVISION));
157 soc_type = SYS_SOC_TYPE(sys_rev);
158 soc_pass = G_SYS_REVISION(sys_rev);
159
160 if (sys_rev_decode()) {
161 prom_printf("Restart after failure to identify SiByte chip\n");
162 machine_restart(NULL);
163 }
164
165 plldiv = G_SYS_PLL_DIV(bus_readq(IOADDR(A_SCD_SYSTEM_CFG)));
166 zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
167
168 prom_printf("Broadcom SiByte %s %s @ %d MHz (SB1 rev %d)\n",
169 soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
170 prom_printf("Board type: %s\n", get_system_type());
171
172 switch(war_pass) {
173 case K_SYS_REVISION_BCM1250_PASS1:
174#ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
175 prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
176 bad_config = 1;
177#endif
178 break;
179 case K_SYS_REVISION_BCM1250_PASS2:
180 /* Pass 2 - easiest as default for now - so many numbers */
181#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
182 prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
183 bad_config = 1;
184#endif
185#ifdef CONFIG_CPU_HAS_PREFETCH
186 prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n");
187 bad_config = 1;
188#endif
189 break;
190 case K_SYS_REVISION_BCM1250_PASS2_2:
191#ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
192 prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n");
193 bad_config = 1;
194#endif
195#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH)
196 prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n");
197#endif
198 break;
199 default:
200 break;
201 }
202 if (bad_config) {
203 prom_printf("Invalid configuration for this chip.\n");
204 machine_restart(NULL);
205 }
206}
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
new file mode 100644
index 000000000000..be91b3990952
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -0,0 +1,98 @@
1/*
2 * Copyright (C) 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/smp.h>
23#include <linux/kernel_stat.h>
24
25#include <asm/mmu_context.h>
26#include <asm/io.h>
27#include <asm/sibyte/sb1250.h>
28#include <asm/sibyte/sb1250_regs.h>
29#include <asm/sibyte/sb1250_int.h>
30
31static void *mailbox_set_regs[] = {
32 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU),
33 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU)
34};
35
36static void *mailbox_clear_regs[] = {
37 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU),
38 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU)
39};
40
41static void *mailbox_regs[] = {
42 (void *)IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
43 (void *)IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
44};
45
46/*
47 * SMP init and finish on secondary CPUs
48 */
49void sb1250_smp_init(void)
50{
51 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
52 STATUSF_IP1 | STATUSF_IP0;
53
54 /* Set interrupt mask, but don't enable */
55 change_c0_status(ST0_IM, imask);
56}
57
58void sb1250_smp_finish(void)
59{
60 extern void sb1250_time_init(void);
61 sb1250_time_init();
62 local_irq_enable();
63}
64
65/*
66 * These are routines for dealing with the sb1250 smp capabilities
67 * independent of board/firmware
68 */
69
70/*
71 * Simple enough; everything is set up, so just poke the appropriate mailbox
72 * register, and we should be set
73 */
74void core_send_ipi(int cpu, unsigned int action)
75{
76 bus_writeq((((u64)action) << 48), mailbox_set_regs[cpu]);
77}
78
79void sb1250_mailbox_interrupt(struct pt_regs *regs)
80{
81 int cpu = smp_processor_id();
82 unsigned int action;
83
84 kstat_this_cpu.irqs[K_INT_MBOX_0]++;
85 /* Load the mailbox register to figure out what we're supposed to do */
86 action = (__bus_readq(mailbox_regs[cpu]) >> 48) & 0xffff;
87
88 /* Clear the mailbox to clear the interrupt */
89 __bus_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]);
90
91 /*
92 * Nothing to do for SMP_RESCHEDULE_YOURSELF; returning from the
93 * interrupt will do the reschedule for us
94 */
95
96 if (action & SMP_CALL_FUNCTION)
97 smp_call_function_interrupt();
98}
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
new file mode 100644
index 000000000000..8b4c848c907b
--- /dev/null
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -0,0 +1,136 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/*
20 * These are routines to set up and handle interrupts from the
21 * sb1250 general purpose timer 0. We're using the timer as a
22 * system clock, so we set it up to run at 100 Hz. On every
23 * interrupt, we update our idea of what the time of day is,
24 * then call do_timer() in the architecture-independent kernel
25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.)
27 */
28#include <linux/config.h>
29#include <linux/interrupt.h>
30#include <linux/sched.h>
31#include <linux/spinlock.h>
32#include <linux/kernel_stat.h>
33
34#include <asm/irq.h>
35#include <asm/ptrace.h>
36#include <asm/addrspace.h>
37#include <asm/time.h>
38#include <asm/io.h>
39
40#include <asm/sibyte/sb1250.h>
41#include <asm/sibyte/sb1250_regs.h>
42#include <asm/sibyte/sb1250_int.h>
43#include <asm/sibyte/sb1250_scd.h>
44
45
46#define IMR_IP2_VAL K_INT_MAP_I0
47#define IMR_IP3_VAL K_INT_MAP_I1
48#define IMR_IP4_VAL K_INT_MAP_I2
49
50extern int sb1250_steal_irq(int irq);
51
52void sb1250_time_init(void)
53{
54 int cpu = smp_processor_id();
55 int irq = K_INT_TIMER_0+cpu;
56
57 /* Only have 4 general purpose timers */
58 if (cpu > 3) {
59 BUG();
60 }
61
62 if (!cpu) {
63 /* Use our own gettimeoffset() routine */
64 do_gettimeoffset = sb1250_gettimeoffset;
65 }
66
67 sb1250_mask_irq(cpu, irq);
68
69 /* Map the timer interrupt to ip[4] of this cpu */
70 bus_writeq(IMR_IP4_VAL,
71 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
72 (irq << 3)));
73
74 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
75 /* Disable the timer and set up the count */
76 bus_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
77#ifdef CONFIG_SIMULATION
78 bus_writeq(50000 / HZ,
79 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
80#else
81 bus_writeq(1000000/HZ,
82 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
83#endif
84
85 /* Set the timer running */
86 bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
87 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
88
89 sb1250_unmask_irq(cpu, irq);
90 sb1250_steal_irq(irq);
91 /*
92 * This interrupt is "special" in that it doesn't use the request_irq
93 * way to hook the irq line. The timer interrupt is initialized early
94 * enough to make this a major pain, and it's also firing enough to
95 * warrant a bit of special case code. sb1250_timer_interrupt is
96 * called directly from irq_handler.S when IP[4] is set during an
97 * interrupt
98 */
99}
100
101void sb1250_timer_interrupt(struct pt_regs *regs)
102{
103 extern asmlinkage void ll_local_timer_interrupt(int irq, struct pt_regs *regs);
104 int cpu = smp_processor_id();
105 int irq = K_INT_TIMER_0 + cpu;
106
107 /* Reset the timer */
108 __bus_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
109 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
110
111 /*
112 * CPU 0 handles the global timer interrupt job
113 */
114 if (cpu == 0) {
115 ll_timer_interrupt(irq, regs);
116 }
117
118 /*
119 * every CPU should do profiling and process accouting
120 */
121 ll_local_timer_interrupt(irq, regs);
122}
123
124/*
125 * We use our own do_gettimeoffset() instead of the generic one,
126 * because the generic one does not work for SMP case.
127 * In addition, since we use general timer 0 for system time,
128 * we can get accurate intra-jiffy offset without calibration.
129 */
130unsigned long sb1250_gettimeoffset(void)
131{
132 unsigned long count =
133 bus_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT)));
134
135 return 1000000/HZ - count;
136 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-20 04:57:25 -0500