aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/sibyte/sb1250/irq.c
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2007-10-22 05:38:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-22 17:09:00 -0400
commitd04533650f64fe3367e180f3e488d92205152cd3 (patch)
tree5f183668d97d9655a8517e61afd46bfa2f80b101 /arch/mips/sibyte/sb1250/irq.c
parent06d428d719dece96c01532b62df4140f4e69a308 (diff)
[MIPS] time: SMP-proofing of Sibyte clockevent/clocksource code.
The BCM148 has 4 cores but there are also just 4 generic timers available so use the ZBbus cycle counter instead of it. In addition the ZBbus counter also offers a much higher resolution and 64-bit counting so I'm considering a later complete conversion to it once I figure out if all members of the Sibyte SOC family support it - the docs seem to agree but the headers files seem to disagree ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/sb1250/irq.c')
-rw-r--r--arch/mips/sibyte/sb1250/irq.c35
1 files changed, 19 insertions, 16 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 500d17e84c09..53780a179d1d 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -402,6 +402,22 @@ static void sb1250_kgdb_interrupt(void)
402 402
403extern void sb1250_mailbox_interrupt(void); 403extern void sb1250_mailbox_interrupt(void);
404 404
405static inline void dispatch_ip2(void)
406{
407 unsigned int cpu = smp_processor_id();
408 unsigned long long mask;
409
410 /*
411 * Default...we've hit an IP[2] interrupt, which means we've got to
412 * check the 1250 interrupt registers to figure out what to do. Need
413 * to detect which CPU we're on, now that smp_affinity is supported.
414 */
415 mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
416 R_IMR_INTERRUPT_STATUS_BASE)));
417 if (mask)
418 do_IRQ(fls64(mask) - 1);
419}
420
405asmlinkage void plat_irq_dispatch(void) 421asmlinkage void plat_irq_dispatch(void)
406{ 422{
407 unsigned int cpu = smp_processor_id(); 423 unsigned int cpu = smp_processor_id();
@@ -434,21 +450,8 @@ asmlinkage void plat_irq_dispatch(void)
434 sb1250_kgdb_interrupt(); 450 sb1250_kgdb_interrupt();
435#endif 451#endif
436 452
437 else if (pending & CAUSEF_IP2) { 453 else if (pending & CAUSEF_IP2)
438 unsigned long long mask; 454 dispatch_ip2();
439 455 else
440 /*
441 * Default...we've hit an IP[2] interrupt, which means we've
442 * got to check the 1250 interrupt registers to figure out what
443 * to do. Need to detect which CPU we're on, now that
444 * smp_affinity is supported.
445 */
446 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
447 R_IMR_INTERRUPT_STATUS_BASE)));
448 if (mask)
449 do_IRQ(fls64(mask) - 1);
450 else
451 spurious_interrupt();
452 } else
453 spurious_interrupt(); 456 spurious_interrupt();
454} 457}