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authorMaciej W. Rozycki <macro@linux-mips.org>2005-02-22 16:51:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:44 -0400
commit65bda1a95d395c256818d1d8129487a4497b29d8 (patch)
tree57bea8a2593b17b987cbc188ecf07c341fda5dbc /arch/mips/sibyte/sb1250/irq.c
parent4912ba72d6e27d0f19ec062ffd00a8c0165a2f67 (diff)
Switch SiByte drivers back to __raw_*() functions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/sb1250/irq.c')
-rw-r--r--arch/mips/sibyte/sb1250/irq.c88
1 files changed, 46 insertions, 42 deletions
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 2725b263cced..a62cba9f32ba 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -96,11 +96,11 @@ void sb1250_mask_irq(int cpu, int irq)
96 u64 cur_ints; 96 u64 cur_ints;
97 97
98 spin_lock_irqsave(&sb1250_imr_lock, flags); 98 spin_lock_irqsave(&sb1250_imr_lock, flags);
99 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + 99 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
100 R_IMR_INTERRUPT_MASK)); 100 R_IMR_INTERRUPT_MASK));
101 cur_ints |= (((u64) 1) << irq); 101 cur_ints |= (((u64) 1) << irq);
102 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 102 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
103 R_IMR_INTERRUPT_MASK)); 103 R_IMR_INTERRUPT_MASK));
104 spin_unlock_irqrestore(&sb1250_imr_lock, flags); 104 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
105} 105}
106 106
@@ -110,11 +110,11 @@ void sb1250_unmask_irq(int cpu, int irq)
110 u64 cur_ints; 110 u64 cur_ints;
111 111
112 spin_lock_irqsave(&sb1250_imr_lock, flags); 112 spin_lock_irqsave(&sb1250_imr_lock, flags);
113 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + 113 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
114 R_IMR_INTERRUPT_MASK)); 114 R_IMR_INTERRUPT_MASK));
115 cur_ints &= ~(((u64) 1) << irq); 115 cur_ints &= ~(((u64) 1) << irq);
116 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 116 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
117 R_IMR_INTERRUPT_MASK)); 117 R_IMR_INTERRUPT_MASK));
118 spin_unlock_irqrestore(&sb1250_imr_lock, flags); 118 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
119} 119}
120 120
@@ -149,23 +149,23 @@ static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
149 149
150 /* Swizzle each CPU's IMR (but leave the IP selection alone) */ 150 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
151 old_cpu = sb1250_irq_owner[irq]; 151 old_cpu = sb1250_irq_owner[irq];
152 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(old_cpu) + 152 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
153 R_IMR_INTERRUPT_MASK)); 153 R_IMR_INTERRUPT_MASK));
154 int_on = !(cur_ints & (((u64) 1) << irq)); 154 int_on = !(cur_ints & (((u64) 1) << irq));
155 if (int_on) { 155 if (int_on) {
156 /* If it was on, mask it */ 156 /* If it was on, mask it */
157 cur_ints |= (((u64) 1) << irq); 157 cur_ints |= (((u64) 1) << irq);
158 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + 158 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
159 R_IMR_INTERRUPT_MASK)); 159 R_IMR_INTERRUPT_MASK));
160 } 160 }
161 sb1250_irq_owner[irq] = cpu; 161 sb1250_irq_owner[irq] = cpu;
162 if (int_on) { 162 if (int_on) {
163 /* unmask for the new CPU */ 163 /* unmask for the new CPU */
164 cur_ints = __bus_readq(IOADDR(A_IMR_MAPPER(cpu) + 164 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
165 R_IMR_INTERRUPT_MASK)); 165 R_IMR_INTERRUPT_MASK));
166 cur_ints &= ~(((u64) 1) << irq); 166 cur_ints &= ~(((u64) 1) << irq);
167 __bus_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + 167 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
168 R_IMR_INTERRUPT_MASK)); 168 R_IMR_INTERRUPT_MASK));
169 } 169 }
170 spin_unlock(&sb1250_imr_lock); 170 spin_unlock(&sb1250_imr_lock);
171 spin_unlock_irqrestore(&desc->lock, flags); 171 spin_unlock_irqrestore(&desc->lock, flags);
@@ -208,8 +208,8 @@ static void ack_sb1250_irq(unsigned int irq)
208 * deliver the interrupts to all CPUs (which makes affinity 208 * deliver the interrupts to all CPUs (which makes affinity
209 * changing easier for us) 209 * changing easier for us)
210 */ 210 */
211 pending = bus_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq], 211 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
212 R_IMR_LDT_INTERRUPT))); 212 R_IMR_LDT_INTERRUPT)));
213 pending &= ((u64)1 << (irq)); 213 pending &= ((u64)1 << (irq));
214 if (pending) { 214 if (pending) {
215 int i; 215 int i;
@@ -224,8 +224,8 @@ static void ack_sb1250_irq(unsigned int irq)
224 * Clear for all CPUs so an affinity switch 224 * Clear for all CPUs so an affinity switch
225 * doesn't find an old status 225 * doesn't find an old status
226 */ 226 */
227 bus_writeq(pending, 227 __raw_writeq(pending,
228 IOADDR(A_IMR_REGISTER(cpu, 228 IOADDR(A_IMR_REGISTER(cpu,
229 R_IMR_LDT_INTERRUPT_CLR))); 229 R_IMR_LDT_INTERRUPT_CLR)));
230 } 230 }
231 231
@@ -340,12 +340,14 @@ void __init arch_init_irq(void)
340 340
341 /* Default everything to IP2 */ 341 /* Default everything to IP2 */
342 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ 342 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
343 bus_writeq(IMR_IP2_VAL, 343 __raw_writeq(IMR_IP2_VAL,
344 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 344 IOADDR(A_IMR_REGISTER(0,
345 (i << 3))); 345 R_IMR_INTERRUPT_MAP_BASE) +
346 bus_writeq(IMR_IP2_VAL, 346 (i << 3)));
347 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + 347 __raw_writeq(IMR_IP2_VAL,
348 (i << 3))); 348 IOADDR(A_IMR_REGISTER(1,
349 R_IMR_INTERRUPT_MAP_BASE) +
350 (i << 3)));
349 } 351 }
350 352
351 init_sb1250_irqs(); 353 init_sb1250_irqs();
@@ -355,23 +357,23 @@ void __init arch_init_irq(void)
355 * inter-cpu messages 357 * inter-cpu messages
356 */ 358 */
357 /* Was I1 */ 359 /* Was I1 */
358 bus_writeq(IMR_IP3_VAL, 360 __raw_writeq(IMR_IP3_VAL,
359 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 361 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
360 (K_INT_MBOX_0 << 3))); 362 (K_INT_MBOX_0 << 3)));
361 bus_writeq(IMR_IP3_VAL, 363 __raw_writeq(IMR_IP3_VAL,
362 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + 364 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
363 (K_INT_MBOX_0 << 3))); 365 (K_INT_MBOX_0 << 3)));
364 366
365 /* Clear the mailboxes. The firmware may leave them dirty */ 367 /* Clear the mailboxes. The firmware may leave them dirty */
366 bus_writeq(0xffffffffffffffffULL, 368 __raw_writeq(0xffffffffffffffffULL,
367 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); 369 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
368 bus_writeq(0xffffffffffffffffULL, 370 __raw_writeq(0xffffffffffffffffULL,
369 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); 371 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
370 372
371 /* Mask everything except the mailbox registers for both cpus */ 373 /* Mask everything except the mailbox registers for both cpus */
372 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); 374 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
373 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); 375 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
374 bus_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); 376 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
375 377
376 sb1250_steal_irq(K_INT_MBOX_0); 378 sb1250_steal_irq(K_INT_MBOX_0);
377 379
@@ -396,12 +398,14 @@ void __init arch_init_irq(void)
396 sb1250_duart_present[kgdb_port] = 0; 398 sb1250_duart_present[kgdb_port] = 0;
397#endif 399#endif
398 /* Setup uart 1 settings, mapper */ 400 /* Setup uart 1 settings, mapper */
399 bus_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port))); 401 __raw_writeq(M_DUART_IMR_BRK,
402 IOADDR(A_DUART_IMRREG(kgdb_port)));
400 403
401 sb1250_steal_irq(kgdb_irq); 404 sb1250_steal_irq(kgdb_irq);
402 bus_writeq(IMR_IP6_VAL, 405 __raw_writeq(IMR_IP6_VAL,
403 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + 406 IOADDR(A_IMR_REGISTER(0,
404 (kgdb_irq<<3))); 407 R_IMR_INTERRUPT_MAP_BASE) +
408 (kgdb_irq << 3)));
405 sb1250_unmask_irq(0, kgdb_irq); 409 sb1250_unmask_irq(0, kgdb_irq);
406 } 410 }
407#endif 411#endif