[MIPS] Sibyte: Delete {sb1250,bcm1480}_steal_irq().

They break the timer interrupt initialization and only seem to be a kludge
for initialization happening in the wrong order.  Further testing done by
Thiemo confirms the suspicion that the other invocations also seem to have
useless.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 0 insertions, 24 deletions

diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 53780a179d1d..52d18fc91f32 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -250,27 +250,6 @@ static struct irqaction sb1250_dummy_action = {
         .dev_id  = 0
 };
 
-int sb1250_steal_irq(int irq)
-{
-        struct irq_desc *desc = irq_desc + irq;
-        unsigned long flags;
-        int retval = 0;
-
-        if (irq >= SB1250_NR_IRQS)
-                return -EINVAL;
-
-        spin_lock_irqsave(&desc->lock, flags);
-        /* Don't allow sharing at all for these */
-        if (desc->action != NULL)
-                retval = -EBUSY;
-        else {
-                desc->action = &sb1250_dummy_action;
-                desc->depth = 0;
-        }
-        spin_unlock_irqrestore(&desc->lock, flags);
-        return 0;
-}
-
 /*
  *  arch_init_irq is called early in the boot sequence from init/main.c via
  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
@@ -342,8 +321,6 @@ void __init arch_init_irq(void)
         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 
-        sb1250_steal_irq(K_INT_MBOX_0);
-
         /*
          * Note that the timer interrupts are also mapped, but this is
          * done in sb1250_time_init().  Also, the profiling driver
@@ -367,7 +344,6 @@ void __init arch_init_irq(void)
                 __raw_writeq(M_DUART_IMR_BRK,
                              IOADDR(A_DUART_IMRREG(kgdb_port)));
 
-                sb1250_steal_irq(kgdb_irq);
                 __raw_writeq(IMR_IP6_VAL,
                              IOADDR(A_IMR_REGISTER(0,
                                                    R_IMR_INTERRUPT_MAP_BASE) +