diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-14 09:02:26 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-16 13:23:45 -0400 |
commit | dd67b1556ebea118b40986cdb8e70874b5454442 (patch) | |
tree | 167320a78cb4afb05d841027d2860f7c38346470 /arch/mips/sgi-ip32 | |
parent | 65a6ec0d72a07f16719e9b7a96e1c4bae044b591 (diff) |
[MIPS] IP32: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sgi-ip32')
-rw-r--r-- | arch/mips/sgi-ip32/ip32-irq.c | 162 | ||||
-rw-r--r-- | arch/mips/sgi-ip32/ip32-setup.c | 2 |
2 files changed, 74 insertions, 90 deletions
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c index 7f4b793c3df3..7e8094f617bf 100644 --- a/arch/mips/sgi-ip32/ip32-irq.c +++ b/arch/mips/sgi-ip32/ip32-irq.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/random.h> | 20 | #include <linux/random.h> |
21 | #include <linux/sched.h> | 21 | #include <linux/sched.h> |
22 | 22 | ||
23 | #include <asm/irq_cpu.h> | ||
23 | #include <asm/mipsregs.h> | 24 | #include <asm/mipsregs.h> |
24 | #include <asm/signal.h> | 25 | #include <asm/signal.h> |
25 | #include <asm/system.h> | 26 | #include <asm/system.h> |
@@ -46,7 +47,8 @@ static void inline flush_mace_bus(void) | |||
46 | #define DBG(x...) | 47 | #define DBG(x...) |
47 | #endif | 48 | #endif |
48 | 49 | ||
49 | /* O2 irq map | 50 | /* |
51 | * O2 irq map | ||
50 | * | 52 | * |
51 | * IP0 -> software (ignored) | 53 | * IP0 -> software (ignored) |
52 | * IP1 -> software (ignored) | 54 | * IP1 -> software (ignored) |
@@ -55,60 +57,60 @@ static void inline flush_mace_bus(void) | |||
55 | * IP4 -> (irq2) X unknown | 57 | * IP4 -> (irq2) X unknown |
56 | * IP5 -> (irq3) X unknown | 58 | * IP5 -> (irq3) X unknown |
57 | * IP6 -> (irq4) X unknown | 59 | * IP6 -> (irq4) X unknown |
58 | * IP7 -> (irq5) 0 CPU count/compare timer (system timer) | 60 | * IP7 -> (irq5) 7 CPU count/compare timer (system timer) |
59 | * | 61 | * |
60 | * crime: (C) | 62 | * crime: (C) |
61 | * | 63 | * |
62 | * CRIME_INT_STAT 31:0: | 64 | * CRIME_INT_STAT 31:0: |
63 | * | 65 | * |
64 | * 0 -> 1 Video in 1 | 66 | * 0 -> 8 Video in 1 |
65 | * 1 -> 2 Video in 2 | 67 | * 1 -> 9 Video in 2 |
66 | * 2 -> 3 Video out | 68 | * 2 -> 10 Video out |
67 | * 3 -> 4 Mace ethernet | 69 | * 3 -> 11 Mace ethernet |
68 | * 4 -> S SuperIO sub-interrupt | 70 | * 4 -> S SuperIO sub-interrupt |
69 | * 5 -> M Miscellaneous sub-interrupt | 71 | * 5 -> M Miscellaneous sub-interrupt |
70 | * 6 -> A Audio sub-interrupt | 72 | * 6 -> A Audio sub-interrupt |
71 | * 7 -> 8 PCI bridge errors | 73 | * 7 -> 15 PCI bridge errors |
72 | * 8 -> 9 PCI SCSI aic7xxx 0 | 74 | * 8 -> 16 PCI SCSI aic7xxx 0 |
73 | * 9 -> 10 PCI SCSI aic7xxx 1 | 75 | * 9 -> 17 PCI SCSI aic7xxx 1 |
74 | * 10 -> 11 PCI slot 0 | 76 | * 10 -> 18 PCI slot 0 |
75 | * 11 -> 12 unused (PCI slot 1) | 77 | * 11 -> 19 unused (PCI slot 1) |
76 | * 12 -> 13 unused (PCI slot 2) | 78 | * 12 -> 20 unused (PCI slot 2) |
77 | * 13 -> 14 unused (PCI shared 0) | 79 | * 13 -> 21 unused (PCI shared 0) |
78 | * 14 -> 15 unused (PCI shared 1) | 80 | * 14 -> 22 unused (PCI shared 1) |
79 | * 15 -> 16 unused (PCI shared 2) | 81 | * 15 -> 23 unused (PCI shared 2) |
80 | * 16 -> 17 GBE0 (E) | 82 | * 16 -> 24 GBE0 (E) |
81 | * 17 -> 18 GBE1 (E) | 83 | * 17 -> 25 GBE1 (E) |
82 | * 18 -> 19 GBE2 (E) | 84 | * 18 -> 26 GBE2 (E) |
83 | * 19 -> 20 GBE3 (E) | 85 | * 19 -> 27 GBE3 (E) |
84 | * 20 -> 21 CPU errors | 86 | * 20 -> 28 CPU errors |
85 | * 21 -> 22 Memory errors | 87 | * 21 -> 29 Memory errors |
86 | * 22 -> 23 RE empty edge (E) | 88 | * 22 -> 30 RE empty edge (E) |
87 | * 23 -> 24 RE full edge (E) | 89 | * 23 -> 31 RE full edge (E) |
88 | * 24 -> 25 RE idle edge (E) | 90 | * 24 -> 32 RE idle edge (E) |
89 | * 25 -> 26 RE empty level | 91 | * 25 -> 33 RE empty level |
90 | * 26 -> 27 RE full level | 92 | * 26 -> 34 RE full level |
91 | * 27 -> 28 RE idle level | 93 | * 27 -> 35 RE idle level |
92 | * 28 -> 29 unused (software 0) (E) | 94 | * 28 -> 36 unused (software 0) (E) |
93 | * 29 -> 30 unused (software 1) (E) | 95 | * 29 -> 37 unused (software 1) (E) |
94 | * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E) | 96 | * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E) |
95 | * 31 -> 32 VICE | 97 | * 31 -> 39 VICE |
96 | * | 98 | * |
97 | * S, M, A: Use the MACE ISA interrupt register | 99 | * S, M, A: Use the MACE ISA interrupt register |
98 | * MACE_ISA_INT_STAT 31:0 | 100 | * MACE_ISA_INT_STAT 31:0 |
99 | * | 101 | * |
100 | * 0-7 -> 33-40 Audio | 102 | * 0-7 -> 40-47 Audio |
101 | * 8 -> 41 RTC | 103 | * 8 -> 48 RTC |
102 | * 9 -> 42 Keyboard | 104 | * 9 -> 49 Keyboard |
103 | * 10 -> X Keyboard polled | 105 | * 10 -> X Keyboard polled |
104 | * 11 -> 44 Mouse | 106 | * 11 -> 51 Mouse |
105 | * 12 -> X Mouse polled | 107 | * 12 -> X Mouse polled |
106 | * 13-15 -> 46-48 Count/compare timers | 108 | * 13-15 -> 53-55 Count/compare timers |
107 | * 16-19 -> 49-52 Parallel (16 E) | 109 | * 16-19 -> 56-59 Parallel (16 E) |
108 | * 20-25 -> 53-58 Serial 1 (22 E) | 110 | * 20-25 -> 60-62 Serial 1 (22 E) |
109 | * 26-31 -> 59-64 Serial 2 (28 E) | 111 | * 26-31 -> 66-71 Serial 2 (28 E) |
110 | * | 112 | * |
111 | * Note that this means IRQs 5-7, 43, and 45 do not exist. This is a | 113 | * Note that this means IRQs 12-14, 50, and 52 do not exist. This is a |
112 | * different IRQ map than IRIX uses, but that's OK as Linux irq handling | 114 | * different IRQ map than IRIX uses, but that's OK as Linux irq handling |
113 | * is quite different anyway. | 115 | * is quite different anyway. |
114 | */ | 116 | */ |
@@ -131,36 +133,6 @@ struct irqaction cpuerr_irq = { | |||
131 | }; | 133 | }; |
132 | 134 | ||
133 | /* | 135 | /* |
134 | * For interrupts wired from a single device to the CPU. Only the clock | ||
135 | * uses this it seems, which is IRQ 0 and IP7. | ||
136 | */ | ||
137 | |||
138 | static void enable_cpu_irq(unsigned int irq) | ||
139 | { | ||
140 | set_c0_status(STATUSF_IP7); | ||
141 | } | ||
142 | |||
143 | static void disable_cpu_irq(unsigned int irq) | ||
144 | { | ||
145 | clear_c0_status(STATUSF_IP7); | ||
146 | } | ||
147 | |||
148 | static void end_cpu_irq(unsigned int irq) | ||
149 | { | ||
150 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | ||
151 | enable_cpu_irq(irq); | ||
152 | } | ||
153 | |||
154 | static struct irq_chip ip32_cpu_interrupt = { | ||
155 | .name = "IP32 CPU", | ||
156 | .ack = disable_cpu_irq, | ||
157 | .mask = disable_cpu_irq, | ||
158 | .mask_ack = disable_cpu_irq, | ||
159 | .unmask = enable_cpu_irq, | ||
160 | .end = end_cpu_irq, | ||
161 | }; | ||
162 | |||
163 | /* | ||
164 | * This is for pure CRIME interrupts - ie not MACE. The advantage? | 136 | * This is for pure CRIME interrupts - ie not MACE. The advantage? |
165 | * We get to split the register in half and do faster lookups. | 137 | * We get to split the register in half and do faster lookups. |
166 | */ | 138 | */ |
@@ -422,15 +394,23 @@ static void ip32_irq0(void) | |||
422 | uint64_t crime_int; | 394 | uint64_t crime_int; |
423 | int irq = 0; | 395 | int irq = 0; |
424 | 396 | ||
397 | /* | ||
398 | * Sanity check interrupt numbering enum. | ||
399 | * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy | ||
400 | * chained. | ||
401 | */ | ||
402 | BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31); | ||
403 | BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31); | ||
404 | |||
425 | crime_int = crime->istat & crime_mask; | 405 | crime_int = crime->istat & crime_mask; |
426 | irq = __ffs(crime_int); | 406 | irq = MACE_VID_IN1_IRQ + __ffs(crime_int); |
427 | crime_int = 1 << irq; | 407 | crime_int = 1 << irq; |
428 | 408 | ||
429 | if (crime_int & CRIME_MACEISA_INT_MASK) { | 409 | if (crime_int & CRIME_MACEISA_INT_MASK) { |
430 | unsigned long mace_int = mace->perif.ctrl.istat; | 410 | unsigned long mace_int = mace->perif.ctrl.istat; |
431 | irq = __ffs(mace_int & maceisa_mask) + 32; | 411 | irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ; |
432 | } | 412 | } |
433 | irq++; | 413 | |
434 | DBG("*irq %u*\n", irq); | 414 | DBG("*irq %u*\n", irq); |
435 | do_IRQ(irq); | 415 | do_IRQ(irq); |
436 | } | 416 | } |
@@ -457,7 +437,7 @@ static void ip32_irq4(void) | |||
457 | 437 | ||
458 | static void ip32_irq5(void) | 438 | static void ip32_irq5(void) |
459 | { | 439 | { |
460 | do_IRQ(IP32_R4K_TIMER_IRQ); | 440 | do_IRQ(MIPS_CPU_IRQ_BASE + 7); |
461 | } | 441 | } |
462 | 442 | ||
463 | asmlinkage void plat_irq_dispatch(void) | 443 | asmlinkage void plat_irq_dispatch(void) |
@@ -490,21 +470,25 @@ void __init arch_init_irq(void) | |||
490 | mace->perif.ctrl.istat = 0; | 470 | mace->perif.ctrl.istat = 0; |
491 | mace->perif.ctrl.imask = 0; | 471 | mace->perif.ctrl.imask = 0; |
492 | 472 | ||
493 | for (irq = 0; irq <= IP32_IRQ_MAX; irq++) { | 473 | mips_cpu_irq_init(); |
494 | struct irq_chip *controller; | 474 | for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) { |
495 | 475 | struct irq_chip *chip; | |
496 | if (irq == IP32_R4K_TIMER_IRQ) | 476 | |
497 | controller = &ip32_cpu_interrupt; | 477 | switch (irq) { |
498 | else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ) | 478 | case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: |
499 | controller = &ip32_mace_interrupt; | 479 | chip = &ip32_mace_interrupt; |
500 | else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ) | 480 | break; |
501 | controller = &ip32_macepci_interrupt; | 481 | case MACEPCI_SCSI0_IRQ ... MACEPCI_SHARED2_IRQ: |
502 | else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ) | 482 | chip = &ip32_macepci_interrupt; |
503 | controller = &ip32_crime_interrupt; | 483 | break; |
504 | else | 484 | case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ: |
505 | controller = &ip32_maceisa_interrupt; | 485 | chip = &ip32_crime_interrupt; |
506 | 486 | break; | |
507 | set_irq_chip(irq, controller); | 487 | default: |
488 | chip = &ip32_maceisa_interrupt; | ||
489 | } | ||
490 | |||
491 | set_irq_chip(irq, chip); | ||
508 | } | 492 | } |
509 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); | 493 | setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); |
510 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); | 494 | setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); |
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c index 4125a5ba119e..fc75bfcb0c0e 100644 --- a/arch/mips/sgi-ip32/ip32-setup.c +++ b/arch/mips/sgi-ip32/ip32-setup.c | |||
@@ -83,7 +83,7 @@ void __init plat_time_init(void) | |||
83 | void __init plat_timer_setup(struct irqaction *irq) | 83 | void __init plat_timer_setup(struct irqaction *irq) |
84 | { | 84 | { |
85 | irq->handler = no_action; | 85 | irq->handler = no_action; |
86 | setup_irq(IP32_R4K_TIMER_IRQ, irq); | 86 | setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); |
87 | } | 87 | } |
88 | 88 | ||
89 | void __init plat_mem_setup(void) | 89 | void __init plat_mem_setup(void) |