diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-02-05 05:52:29 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-02-05 05:52:29 -0500 |
commit | 59a675b22026e29e7f281d7b832de67dd8559b83 (patch) | |
tree | 2f4174947b04a7e988cc476414ecafb5f7c46dbb /arch/mips/sgi-ip32 | |
parent | 9b4a1617772d6d5ab5eeda0cd95302fae119e359 (diff) |
[SERIAL] uart_port flags member should use UPF_*
Convert usage of ASYNC_* to UPF_*.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/mips/sgi-ip32')
-rw-r--r-- | arch/mips/sgi-ip32/ip32-setup.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c index d10a269aeae1..2c38770b1e1b 100644 --- a/arch/mips/sgi-ip32/ip32-setup.c +++ b/arch/mips/sgi-ip32/ip32-setup.c | |||
@@ -66,11 +66,6 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str) | |||
66 | #include <linux/tty.h> | 66 | #include <linux/tty.h> |
67 | #include <linux/serial.h> | 67 | #include <linux/serial.h> |
68 | #include <linux/serial_core.h> | 68 | #include <linux/serial_core.h> |
69 | extern int early_serial_setup(struct uart_port *port); | ||
70 | |||
71 | #define STD_COM_FLAGS (ASYNC_SKIP_TEST) | ||
72 | #define BASE_BAUD (1843200 / 16) | ||
73 | |||
74 | #endif /* CONFIG_SERIAL_8250 */ | 69 | #endif /* CONFIG_SERIAL_8250 */ |
75 | 70 | ||
76 | /* An arbitrary time; this can be decreased if reliability looks good */ | 71 | /* An arbitrary time; this can be decreased if reliability looks good */ |
@@ -110,8 +105,8 @@ void __init plat_setup(void) | |||
110 | o2_serial[0].type = PORT_16550A; | 105 | o2_serial[0].type = PORT_16550A; |
111 | o2_serial[0].line = 0; | 106 | o2_serial[0].line = 0; |
112 | o2_serial[0].irq = MACEISA_SERIAL1_IRQ; | 107 | o2_serial[0].irq = MACEISA_SERIAL1_IRQ; |
113 | o2_serial[0].flags = STD_COM_FLAGS; | 108 | o2_serial[0].flags = UPF_SKIP_TEST; |
114 | o2_serial[0].uartclk = BASE_BAUD * 16; | 109 | o2_serial[0].uartclk = 1843200; |
115 | o2_serial[0].iotype = UPIO_MEM; | 110 | o2_serial[0].iotype = UPIO_MEM; |
116 | o2_serial[0].membase = (char *)&mace->isa.serial1; | 111 | o2_serial[0].membase = (char *)&mace->isa.serial1; |
117 | o2_serial[0].fifosize = 14; | 112 | o2_serial[0].fifosize = 14; |
@@ -121,8 +116,8 @@ void __init plat_setup(void) | |||
121 | o2_serial[1].type = PORT_16550A; | 116 | o2_serial[1].type = PORT_16550A; |
122 | o2_serial[1].line = 1; | 117 | o2_serial[1].line = 1; |
123 | o2_serial[1].irq = MACEISA_SERIAL2_IRQ; | 118 | o2_serial[1].irq = MACEISA_SERIAL2_IRQ; |
124 | o2_serial[1].flags = STD_COM_FLAGS; | 119 | o2_serial[1].flags = UPF_SKIP_TEST; |
125 | o2_serial[1].uartclk = BASE_BAUD * 16; | 120 | o2_serial[1].uartclk = 1843200; |
126 | o2_serial[1].iotype = UPIO_MEM; | 121 | o2_serial[1].iotype = UPIO_MEM; |
127 | o2_serial[1].membase = (char *)&mace->isa.serial2; | 122 | o2_serial[1].membase = (char *)&mace->isa.serial2; |
128 | o2_serial[1].fifosize = 14; | 123 | o2_serial[1].fifosize = 14; |