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authorRalf Baechle <ralf@linux-mips.org>2006-10-07 14:44:33 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-10-07 21:38:28 -0400
commit937a801576f954bd030d7c4a5a94571710d87c0b (patch)
tree48d3440f765b56cf32a89b4b8193dd033d8227a8 /arch/mips/sgi-ip32/ip32-irq.c
parent31aa36658a123263a9a69896e348b9600e050679 (diff)
[MIPS] Complete fixes after removal of pt_regs argument to int handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sgi-ip32/ip32-irq.c')
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c48
1 files changed, 23 insertions, 25 deletions
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c64a820373de..c9acadd0846b 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -120,10 +120,8 @@ static void inline flush_mace_bus(void)
120static DEFINE_SPINLOCK(ip32_irq_lock); 120static DEFINE_SPINLOCK(ip32_irq_lock);
121 121
122/* Some initial interrupts to set up */ 122/* Some initial interrupts to set up */
123extern irqreturn_t crime_memerr_intr (int irq, void *dev_id, 123extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
124 struct pt_regs *regs); 124extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
125extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id,
126 struct pt_regs *regs);
127 125
128struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, 126struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED,
129 CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; 127 CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
@@ -479,7 +477,7 @@ static struct irq_chip ip32_mace_interrupt = {
479 .end = end_mace_irq, 477 .end = end_mace_irq,
480}; 478};
481 479
482static void ip32_unknown_interrupt(struct pt_regs *regs) 480static void ip32_unknown_interrupt(void)
483{ 481{
484 printk ("Unknown interrupt occurred!\n"); 482 printk ("Unknown interrupt occurred!\n");
485 printk ("cp0_status: %08x\n", read_c0_status()); 483 printk ("cp0_status: %08x\n", read_c0_status());
@@ -492,7 +490,7 @@ static void ip32_unknown_interrupt(struct pt_regs *regs)
492 printk ("MACE PCI control register: %08x\n", mace->pci.control); 490 printk ("MACE PCI control register: %08x\n", mace->pci.control);
493 491
494 printk("Register dump:\n"); 492 printk("Register dump:\n");
495 show_regs(regs); 493 show_regs(get_irq_regs());
496 494
497 printk("Please mail this report to linux-mips@linux-mips.org\n"); 495 printk("Please mail this report to linux-mips@linux-mips.org\n");
498 printk("Spinning..."); 496 printk("Spinning...");
@@ -501,7 +499,7 @@ static void ip32_unknown_interrupt(struct pt_regs *regs)
501 499
502/* CRIME 1.1 appears to deliver all interrupts to this one pin. */ 500/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
503/* change this to loop over all edge-triggered irqs, exception masked out ones */ 501/* change this to loop over all edge-triggered irqs, exception masked out ones */
504static void ip32_irq0(struct pt_regs *regs) 502static void ip32_irq0(void)
505{ 503{
506 uint64_t crime_int; 504 uint64_t crime_int;
507 int irq = 0; 505 int irq = 0;
@@ -516,50 +514,50 @@ static void ip32_irq0(struct pt_regs *regs)
516 } 514 }
517 irq++; 515 irq++;
518 DBG("*irq %u*\n", irq); 516 DBG("*irq %u*\n", irq);
519 do_IRQ(irq, regs); 517 do_IRQ(irq);
520} 518}
521 519
522static void ip32_irq1(struct pt_regs *regs) 520static void ip32_irq1(void)
523{ 521{
524 ip32_unknown_interrupt(regs); 522 ip32_unknown_interrupt();
525} 523}
526 524
527static void ip32_irq2(struct pt_regs *regs) 525static void ip32_irq2(void)
528{ 526{
529 ip32_unknown_interrupt(regs); 527 ip32_unknown_interrupt();
530} 528}
531 529
532static void ip32_irq3(struct pt_regs *regs) 530static void ip32_irq3(void)
533{ 531{
534 ip32_unknown_interrupt(regs); 532 ip32_unknown_interrupt();
535} 533}
536 534
537static void ip32_irq4(struct pt_regs *regs) 535static void ip32_irq4(void)
538{ 536{
539 ip32_unknown_interrupt(regs); 537 ip32_unknown_interrupt();
540} 538}
541 539
542static void ip32_irq5(struct pt_regs *regs) 540static void ip32_irq5(void)
543{ 541{
544 ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs); 542 ll_timer_interrupt(IP32_R4K_TIMER_IRQ);
545} 543}
546 544
547asmlinkage void plat_irq_dispatch(struct pt_regs *regs) 545asmlinkage void plat_irq_dispatch(void)
548{ 546{
549 unsigned int pending = read_c0_cause(); 547 unsigned int pending = read_c0_cause();
550 548
551 if (likely(pending & IE_IRQ0)) 549 if (likely(pending & IE_IRQ0))
552 ip32_irq0(regs); 550 ip32_irq0();
553 else if (unlikely(pending & IE_IRQ1)) 551 else if (unlikely(pending & IE_IRQ1))
554 ip32_irq1(regs); 552 ip32_irq1();
555 else if (unlikely(pending & IE_IRQ2)) 553 else if (unlikely(pending & IE_IRQ2))
556 ip32_irq2(regs); 554 ip32_irq2();
557 else if (unlikely(pending & IE_IRQ3)) 555 else if (unlikely(pending & IE_IRQ3))
558 ip32_irq3(regs); 556 ip32_irq3();
559 else if (unlikely(pending & IE_IRQ4)) 557 else if (unlikely(pending & IE_IRQ4))
560 ip32_irq4(regs); 558 ip32_irq4();
561 else if (likely(pending & IE_IRQ5)) 559 else if (likely(pending & IE_IRQ5))
562 ip32_irq5(regs); 560 ip32_irq5();
563} 561}
564 562
565void __init arch_init_irq(void) 563void __init arch_init_irq(void)