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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/sgi-ip22/ip22-mc.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/sgi-ip22/ip22-mc.c')
-rw-r--r--arch/mips/sgi-ip22/ip22-mc.c208
1 files changed, 208 insertions, 0 deletions
diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
new file mode 100644
index 000000000000..b58bd522262b
--- /dev/null
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -0,0 +1,208 @@
1/*
2 * ip22-mc.c: Routines for manipulating SGI Memory Controller.
3 *
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
5 * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu) - Indigo2 changes
6 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/kernel.h>
12
13#include <asm/io.h>
14#include <asm/bootinfo.h>
15#include <asm/sgialib.h>
16#include <asm/sgi/mc.h>
17#include <asm/sgi/hpc3.h>
18#include <asm/sgi/ip22.h>
19
20struct sgimc_regs *sgimc;
21
22EXPORT_SYMBOL(sgimc);
23
24static inline unsigned long get_bank_addr(unsigned int memconfig)
25{
26 return ((memconfig & SGIMC_MCONFIG_BASEADDR) <<
27 ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 24 : 22));
28}
29
30static inline unsigned long get_bank_size(unsigned int memconfig)
31{
32 return ((memconfig & SGIMC_MCONFIG_RMASK) + 0x0100) <<
33 ((sgimc->systemid & SGIMC_SYSID_MASKREV) >= 5 ? 16 : 14);
34}
35
36static inline unsigned int get_bank_config(int bank)
37{
38 unsigned int res = bank > 1 ? sgimc->mconfig1 : sgimc->mconfig0;
39 return bank % 2 ? res & 0xffff : res >> 16;
40}
41
42struct mem {
43 unsigned long addr;
44 unsigned long size;
45};
46
47/*
48 * Detect installed memory, do some sanity checks and notify kernel about it
49 */
50static void probe_memory(void)
51{
52 int i, j, found, cnt = 0;
53 struct mem bank[4];
54 struct mem space[2] = {{SGIMC_SEG0_BADDR, 0}, {SGIMC_SEG1_BADDR, 0}};
55
56 printk(KERN_INFO "MC: Probing memory configuration:\n");
57 for (i = 0; i < ARRAY_SIZE(bank); i++) {
58 unsigned int tmp = get_bank_config(i);
59 if (!(tmp & SGIMC_MCONFIG_BVALID))
60 continue;
61
62 bank[cnt].size = get_bank_size(tmp);
63 bank[cnt].addr = get_bank_addr(tmp);
64 printk(KERN_INFO " bank%d: %3ldM @ %08lx\n",
65 i, bank[cnt].size / 1024 / 1024, bank[cnt].addr);
66 cnt++;
67 }
68
69 /* And you thought bubble sort is dead algorithm... */
70 do {
71 unsigned long addr, size;
72
73 found = 0;
74 for (i = 1; i < cnt; i++)
75 if (bank[i-1].addr > bank[i].addr) {
76 addr = bank[i].addr;
77 size = bank[i].size;
78 bank[i].addr = bank[i-1].addr;
79 bank[i].size = bank[i-1].size;
80 bank[i-1].addr = addr;
81 bank[i-1].size = size;
82 found = 1;
83 }
84 } while (found);
85
86 /* Figure out how are memory banks mapped into spaces */
87 for (i = 0; i < cnt; i++) {
88 found = 0;
89 for (j = 0; j < ARRAY_SIZE(space) && !found; j++)
90 if (space[j].addr + space[j].size == bank[i].addr) {
91 space[j].size += bank[i].size;
92 found = 1;
93 }
94 /* There is either hole or overlapping memory */
95 if (!found)
96 printk(KERN_CRIT "MC: Memory configuration mismatch "
97 "(%08lx), expect Bus Error soon\n",
98 bank[i].addr);
99 }
100
101 for (i = 0; i < ARRAY_SIZE(space); i++)
102 if (space[i].size)
103 add_memory_region(space[i].addr, space[i].size,
104 BOOT_MEM_RAM);
105}
106
107void __init sgimc_init(void)
108{
109 u32 tmp;
110
111 /* ioremap can't fail */
112 sgimc = (struct sgimc_regs *)
113 ioremap(SGIMC_BASE, sizeof(struct sgimc_regs));
114
115 printk(KERN_INFO "MC: SGI memory controller Revision %d\n",
116 (int) sgimc->systemid & SGIMC_SYSID_MASKREV);
117
118 /* Place the MC into a known state. This must be done before
119 * interrupts are first enabled etc.
120 */
121
122 /* Step 0: Make sure we turn off the watchdog in case it's
123 * still running (which might be the case after a
124 * soft reboot).
125 */
126 tmp = sgimc->cpuctrl0;
127 tmp &= ~SGIMC_CCTRL0_WDOG;
128 sgimc->cpuctrl0 = tmp;
129
130 /* Step 1: The CPU/GIO error status registers will not latch
131 * up a new error status until the register has been
132 * cleared by the cpu. These status registers are
133 * cleared by writing any value to them.
134 */
135 sgimc->cstat = sgimc->gstat = 0;
136
137 /* Step 2: Enable all parity checking in cpu control register
138 * zero.
139 */
140 tmp = sgimc->cpuctrl0;
141 tmp |= (SGIMC_CCTRL0_EPERRGIO | SGIMC_CCTRL0_EPERRMEM |
142 SGIMC_CCTRL0_R4KNOCHKPARR);
143 sgimc->cpuctrl0 = tmp;
144
145 /* Step 3: Setup the MC write buffer depth, this is controlled
146 * in cpu control register 1 in the lower 4 bits.
147 */
148 tmp = sgimc->cpuctrl1;
149 tmp &= ~0xf;
150 tmp |= 0xd;
151 sgimc->cpuctrl1 = tmp;
152
153 /* Step 4: Initialize the RPSS divider register to run as fast
154 * as it can correctly operate. The register is laid
155 * out as follows:
156 *
157 * ----------------------------------------
158 * | RESERVED | INCREMENT | DIVIDER |
159 * ----------------------------------------
160 * 31 16 15 8 7 0
161 *
162 * DIVIDER determines how often a 'tick' happens,
163 * INCREMENT determines by how the RPSS increment
164 * registers value increases at each 'tick'. Thus,
165 * for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
166 */
167 sgimc->divider = 0x101;
168
169 /* Step 5: Initialize GIO64 arbitrator configuration register.
170 *
171 * NOTE: HPC init code in sgihpc_init() must run before us because
172 * we need to know Guiness vs. FullHouse and the board
173 * revision on this machine. You have been warned.
174 */
175
176 /* First the basic invariants across all GIO64 implementations. */
177 tmp = SGIMC_GIOPAR_HPC64; /* All 1st HPC's interface at 64bits */
178 tmp |= SGIMC_GIOPAR_ONEBUS; /* Only one physical GIO bus exists */
179
180 if (ip22_is_fullhouse()) {
181 /* Fullhouse specific settings. */
182 if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
183 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC at 64bits */
184 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp0 pipelines */
185 tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
186 tmp |= SGIMC_GIOPAR_RTIMEEXP0; /* exp0 is realtime */
187 } else {
188 tmp |= SGIMC_GIOPAR_HPC264; /* 2nd HPC 64bits */
189 tmp |= SGIMC_GIOPAR_PLINEEXP0; /* exp[01] pipelined */
190 tmp |= SGIMC_GIOPAR_PLINEEXP1;
191 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
192 tmp |= SGIMC_GIOPAR_GFX64; /* GFX at 64 bits */
193 }
194 } else {
195 /* Guiness specific settings. */
196 tmp |= SGIMC_GIOPAR_EISA64; /* MC talks to EISA at 64bits */
197 tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
198 }
199 sgimc->giopar = tmp; /* poof */
200
201 probe_memory();
202}
203
204void __init prom_meminit(void) {}
205unsigned long __init prom_free_prom_memory(void)
206{
207 return 0;
208}