[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 3 deletions

diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 18348321795d..338c0d706988 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -20,10 +20,10 @@
 #include <asm/mipsregs.h>
 #include <asm/addrspace.h>
 #include <asm/irq_cpu.h>
-
 #include <asm/sgi/ioc.h>
 #include <asm/sgi/hpc3.h>
 #include <asm/sgi/ip22.h>
+#include <asm/time.h>
 
 /* #define DEBUG_SGINT */
 
@@ -204,7 +204,6 @@ static struct irqaction map1_cascade = {
 #define SGI_INTERRUPTS  SGINT_LOCAL3
 #endif
 
-extern void indy_r4k_timer_interrupt(void);
 extern void indy_8254timer_irq(void);
 
 /*
@@ -243,7 +242,7 @@ asmlinkage void plat_irq_dispatch(void)
          * First we check for r4k counter/timer IRQ.
          */
         if (pending & CAUSEF_IP7)
-                indy_r4k_timer_interrupt();
+                ll_timer_interrupt(SGI_TIMER_IRQ, NULL);
         else if (pending & CAUSEF_IP2)
                 indy_local0_irqdispatch();
         else if (pending & CAUSEF_IP3)