diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-12-23 10:23:23 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-12-23 10:23:23 -0500 |
commit | 1ccedb7cdba6886939dd8b4c8f965a826f696e56 (patch) | |
tree | 0f5fc519a68faca5318c296315c9b6c502907056 /arch/mips/rb532 | |
parent | a98f8fd24fb24fcb9a359553e64dd6aac5cf4279 (diff) | |
parent | 929096fe9ff1f4b3645cf3919527ab47e8d5e17c (diff) |
Merge commit 'v2.6.28-rc9' into x86/apic
Diffstat (limited to 'arch/mips/rb532')
-rw-r--r-- | arch/mips/rb532/devices.c | 2 | ||||
-rw-r--r-- | arch/mips/rb532/gpio.c | 193 |
2 files changed, 74 insertions, 121 deletions
diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 2f22d714d5b0..c1c29181bd46 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c | |||
@@ -118,7 +118,7 @@ static struct platform_device cf_slot0 = { | |||
118 | /* Resources and device for NAND */ | 118 | /* Resources and device for NAND */ |
119 | static int rb532_dev_ready(struct mtd_info *mtd) | 119 | static int rb532_dev_ready(struct mtd_info *mtd) |
120 | { | 120 | { |
121 | return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; | 121 | return gpio_get_value(GPIO_RDY); |
122 | } | 122 | } |
123 | 123 | ||
124 | static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | 124 | static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 70c4a6726377..0e84c8ab6a39 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c | |||
@@ -39,10 +39,6 @@ | |||
39 | struct rb532_gpio_chip { | 39 | struct rb532_gpio_chip { |
40 | struct gpio_chip chip; | 40 | struct gpio_chip chip; |
41 | void __iomem *regbase; | 41 | void __iomem *regbase; |
42 | void (*set_int_level)(struct gpio_chip *chip, unsigned offset, int value); | ||
43 | int (*get_int_level)(struct gpio_chip *chip, unsigned offset); | ||
44 | void (*set_int_status)(struct gpio_chip *chip, unsigned offset, int value); | ||
45 | int (*get_int_status)(struct gpio_chip *chip, unsigned offset); | ||
46 | }; | 42 | }; |
47 | 43 | ||
48 | struct mpmc_device dev3; | 44 | struct mpmc_device dev3; |
@@ -111,15 +107,47 @@ unsigned char get_latch_u5(void) | |||
111 | } | 107 | } |
112 | EXPORT_SYMBOL(get_latch_u5); | 108 | EXPORT_SYMBOL(get_latch_u5); |
113 | 109 | ||
110 | /* rb532_set_bit - sanely set a bit | ||
111 | * | ||
112 | * bitval: new value for the bit | ||
113 | * offset: bit index in the 4 byte address range | ||
114 | * ioaddr: 4 byte aligned address being altered | ||
115 | */ | ||
116 | static inline void rb532_set_bit(unsigned bitval, | ||
117 | unsigned offset, void __iomem *ioaddr) | ||
118 | { | ||
119 | unsigned long flags; | ||
120 | u32 val; | ||
121 | |||
122 | bitval = !!bitval; /* map parameter to {0,1} */ | ||
123 | |||
124 | local_irq_save(flags); | ||
125 | |||
126 | val = readl(ioaddr); | ||
127 | val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */ | ||
128 | val |= ( bitval << offset ); /* set bit if bitval == 1 */ | ||
129 | writel(val, ioaddr); | ||
130 | |||
131 | local_irq_restore(flags); | ||
132 | } | ||
133 | |||
134 | /* rb532_get_bit - read a bit | ||
135 | * | ||
136 | * returns the boolean state of the bit, which may be > 1 | ||
137 | */ | ||
138 | static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) | ||
139 | { | ||
140 | return (readl(ioaddr) & (1 << offset)); | ||
141 | } | ||
142 | |||
114 | /* | 143 | /* |
115 | * Return GPIO level */ | 144 | * Return GPIO level */ |
116 | static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) | 145 | static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) |
117 | { | 146 | { |
118 | u32 mask = 1 << offset; | ||
119 | struct rb532_gpio_chip *gpch; | 147 | struct rb532_gpio_chip *gpch; |
120 | 148 | ||
121 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | 149 | gpch = container_of(chip, struct rb532_gpio_chip, chip); |
122 | return readl(gpch->regbase + GPIOD) & mask; | 150 | return rb532_get_bit(offset, gpch->regbase + GPIOD); |
123 | } | 151 | } |
124 | 152 | ||
125 | /* | 153 | /* |
@@ -128,23 +156,10 @@ static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) | |||
128 | static void rb532_gpio_set(struct gpio_chip *chip, | 156 | static void rb532_gpio_set(struct gpio_chip *chip, |
129 | unsigned offset, int value) | 157 | unsigned offset, int value) |
130 | { | 158 | { |
131 | unsigned long flags; | ||
132 | u32 mask = 1 << offset; | ||
133 | u32 tmp; | ||
134 | struct rb532_gpio_chip *gpch; | 159 | struct rb532_gpio_chip *gpch; |
135 | void __iomem *gpvr; | ||
136 | 160 | ||
137 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | 161 | gpch = container_of(chip, struct rb532_gpio_chip, chip); |
138 | gpvr = gpch->regbase + GPIOD; | 162 | rb532_set_bit(value, offset, gpch->regbase + GPIOD); |
139 | |||
140 | local_irq_save(flags); | ||
141 | tmp = readl(gpvr); | ||
142 | if (value) | ||
143 | tmp |= mask; | ||
144 | else | ||
145 | tmp &= ~mask; | ||
146 | writel(tmp, gpvr); | ||
147 | local_irq_restore(flags); | ||
148 | } | 163 | } |
149 | 164 | ||
150 | /* | 165 | /* |
@@ -152,21 +167,14 @@ static void rb532_gpio_set(struct gpio_chip *chip, | |||
152 | */ | 167 | */ |
153 | static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | 168 | static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
154 | { | 169 | { |
155 | unsigned long flags; | ||
156 | u32 mask = 1 << offset; | ||
157 | u32 value; | ||
158 | struct rb532_gpio_chip *gpch; | 170 | struct rb532_gpio_chip *gpch; |
159 | void __iomem *gpdr; | ||
160 | 171 | ||
161 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | 172 | gpch = container_of(chip, struct rb532_gpio_chip, chip); |
162 | gpdr = gpch->regbase + GPIOCFG; | ||
163 | 173 | ||
164 | local_irq_save(flags); | 174 | if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) |
165 | value = readl(gpdr); | 175 | return 1; /* alternate function, GPIOCFG is ignored */ |
166 | value &= ~mask; | ||
167 | writel(value, gpdr); | ||
168 | local_irq_restore(flags); | ||
169 | 176 | ||
177 | rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); | ||
170 | return 0; | 178 | return 0; |
171 | } | 179 | } |
172 | 180 | ||
@@ -176,117 +184,60 @@ static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |||
176 | static int rb532_gpio_direction_output(struct gpio_chip *chip, | 184 | static int rb532_gpio_direction_output(struct gpio_chip *chip, |
177 | unsigned offset, int value) | 185 | unsigned offset, int value) |
178 | { | 186 | { |
179 | unsigned long flags; | ||
180 | u32 mask = 1 << offset; | ||
181 | u32 tmp; | ||
182 | struct rb532_gpio_chip *gpch; | 187 | struct rb532_gpio_chip *gpch; |
183 | void __iomem *gpdr; | ||
184 | 188 | ||
185 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | 189 | gpch = container_of(chip, struct rb532_gpio_chip, chip); |
186 | writel(mask, gpch->regbase + GPIOD); | ||
187 | gpdr = gpch->regbase + GPIOCFG; | ||
188 | 190 | ||
189 | local_irq_save(flags); | 191 | if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) |
190 | tmp = readl(gpdr); | 192 | return 1; /* alternate function, GPIOCFG is ignored */ |
191 | tmp |= mask; | ||
192 | writel(tmp, gpdr); | ||
193 | local_irq_restore(flags); | ||
194 | 193 | ||
194 | /* set the initial output value */ | ||
195 | rb532_set_bit(value, offset, gpch->regbase + GPIOD); | ||
196 | |||
197 | rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); | ||
195 | return 0; | 198 | return 0; |
196 | } | 199 | } |
197 | 200 | ||
198 | /* | 201 | static struct rb532_gpio_chip rb532_gpio_chip[] = { |
199 | * Set the GPIO interrupt level | 202 | [0] = { |
200 | */ | 203 | .chip = { |
201 | static void rb532_gpio_set_int_level(struct gpio_chip *chip, | 204 | .label = "gpio0", |
202 | unsigned offset, int value) | 205 | .direction_input = rb532_gpio_direction_input, |
203 | { | 206 | .direction_output = rb532_gpio_direction_output, |
204 | unsigned long flags; | 207 | .get = rb532_gpio_get, |
205 | u32 mask = 1 << offset; | 208 | .set = rb532_gpio_set, |
206 | u32 tmp; | 209 | .base = 0, |
207 | struct rb532_gpio_chip *gpch; | 210 | .ngpio = 32, |
208 | void __iomem *gpil; | 211 | }, |
209 | 212 | }, | |
210 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | 213 | }; |
211 | gpil = gpch->regbase + GPIOILEVEL; | ||
212 | |||
213 | local_irq_save(flags); | ||
214 | tmp = readl(gpil); | ||
215 | if (value) | ||
216 | tmp |= mask; | ||
217 | else | ||
218 | tmp &= ~mask; | ||
219 | writel(tmp, gpil); | ||
220 | local_irq_restore(flags); | ||
221 | } | ||
222 | 214 | ||
223 | /* | 215 | /* |
224 | * Get the GPIO interrupt level | 216 | * Set GPIO interrupt level |
225 | */ | 217 | */ |
226 | static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset) | 218 | void rb532_gpio_set_ilevel(int bit, unsigned gpio) |
227 | { | 219 | { |
228 | u32 mask = 1 << offset; | 220 | rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); |
229 | struct rb532_gpio_chip *gpch; | ||
230 | |||
231 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | ||
232 | return readl(gpch->regbase + GPIOILEVEL) & mask; | ||
233 | } | 221 | } |
222 | EXPORT_SYMBOL(rb532_gpio_set_ilevel); | ||
234 | 223 | ||
235 | /* | 224 | /* |
236 | * Set the GPIO interrupt status | 225 | * Set GPIO interrupt status |
237 | */ | 226 | */ |
238 | static void rb532_gpio_set_int_status(struct gpio_chip *chip, | 227 | void rb532_gpio_set_istat(int bit, unsigned gpio) |
239 | unsigned offset, int value) | ||
240 | { | 228 | { |
241 | unsigned long flags; | 229 | rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); |
242 | u32 mask = 1 << offset; | ||
243 | u32 tmp; | ||
244 | struct rb532_gpio_chip *gpch; | ||
245 | void __iomem *gpis; | ||
246 | |||
247 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | ||
248 | gpis = gpch->regbase + GPIOISTAT; | ||
249 | |||
250 | local_irq_save(flags); | ||
251 | tmp = readl(gpis); | ||
252 | if (value) | ||
253 | tmp |= mask; | ||
254 | else | ||
255 | tmp &= ~mask; | ||
256 | writel(tmp, gpis); | ||
257 | local_irq_restore(flags); | ||
258 | } | 230 | } |
231 | EXPORT_SYMBOL(rb532_gpio_set_istat); | ||
259 | 232 | ||
260 | /* | 233 | /* |
261 | * Get the GPIO interrupt status | 234 | * Configure GPIO alternate function |
262 | */ | 235 | */ |
263 | static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset) | 236 | static void rb532_gpio_set_func(int bit, unsigned gpio) |
264 | { | 237 | { |
265 | u32 mask = 1 << offset; | 238 | rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); |
266 | struct rb532_gpio_chip *gpch; | ||
267 | |||
268 | gpch = container_of(chip, struct rb532_gpio_chip, chip); | ||
269 | return readl(gpch->regbase + GPIOISTAT) & mask; | ||
270 | } | 239 | } |
271 | 240 | ||
272 | static struct rb532_gpio_chip rb532_gpio_chip[] = { | ||
273 | [0] = { | ||
274 | .chip = { | ||
275 | .label = "gpio0", | ||
276 | .direction_input = rb532_gpio_direction_input, | ||
277 | .direction_output = rb532_gpio_direction_output, | ||
278 | .get = rb532_gpio_get, | ||
279 | .set = rb532_gpio_set, | ||
280 | .base = 0, | ||
281 | .ngpio = 32, | ||
282 | }, | ||
283 | .get_int_level = rb532_gpio_get_int_level, | ||
284 | .set_int_level = rb532_gpio_set_int_level, | ||
285 | .get_int_status = rb532_gpio_get_int_status, | ||
286 | .set_int_status = rb532_gpio_set_int_status, | ||
287 | }, | ||
288 | }; | ||
289 | |||
290 | int __init rb532_gpio_init(void) | 241 | int __init rb532_gpio_init(void) |
291 | { | 242 | { |
292 | struct resource *r; | 243 | struct resource *r; |
@@ -310,9 +261,11 @@ int __init rb532_gpio_init(void) | |||
310 | return -ENXIO; | 261 | return -ENXIO; |
311 | } | 262 | } |
312 | 263 | ||
313 | /* Set the interrupt status and level for the CF pin */ | 264 | /* configure CF_GPIO_NUM as CFRDY IRQ source */ |
314 | rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1); | 265 | rb532_gpio_set_func(0, CF_GPIO_NUM); |
315 | rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0); | 266 | rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); |
267 | rb532_gpio_set_ilevel(1, CF_GPIO_NUM); | ||
268 | rb532_gpio_set_istat(0, CF_GPIO_NUM); | ||
316 | 269 | ||
317 | return 0; | 270 | return 0; |
318 | } | 271 | } |