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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-10 10:48:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-10 10:48:05 -0400
commitdaf799cca8abbf7f3e253ecf1d41d244070773d7 (patch)
tree6fb27ff60b820ae0eeb906c8a5d8d7f93f89cd8b /arch/mips/ralink
parent6019958d146a4f127dae727a930f902c92531e6e (diff)
parentb22d1b6a91ca4260f869e349179ae53f18c664db (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: - More work on DT support for various platforms - Various fixes that were to late to make it straight into 3.9 - Improved platform support, in particular the Netlogic XLR and BCM63xx, and the SEAD3 and Malta eval boards. - Support for several Ralink SOC families. - Complete support for the microMIPS ASE which basically reencodes the existing MIPS32/MIPS64 ISA to use non-constant size instructions. - Some fallout from LTO work which remove old cruft and will generally make the MIPS kernel easier to maintain and resistant to compiler optimization, even in absence of LTO. - KVM support. While MIPS has announced hardware virtualization extensions this KVM extension uses trap and emulate mode for virtualization of MIPS32. More KVM work to add support for VZ hardware virtualizaiton extensions and MIPS64 will probably already be merged for 3.11. Most of this has been sitting in -next for a long time. All defconfigs have been build or run time tested except three for which fixes are being sent by other maintainers. Semantic conflict with kvm updates done as per Ralf * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (118 commits) MIPS: Add new GIC clockevent driver. MIPS: Formatting clean-ups for clocksources. MIPS: Refactor GIC clocksource code. MIPS: Move 'gic_frequency' to common location. MIPS: Move 'gic_present' to common location. MIPS: MIPS16e: Add unaligned access support. MIPS: MIPS16e: Support handling of delay slots. MIPS: MIPS16e: Add instruction formats. MIPS: microMIPS: Optimise 'strnlen' core library function. MIPS: microMIPS: Optimise 'strlen' core library function. MIPS: microMIPS: Optimise 'strncpy' core library function. MIPS: microMIPS: Optimise 'memset' core library function. MIPS: microMIPS: Add configuration option for microMIPS kernel. MIPS: microMIPS: Disable LL/SC and fix linker bug. MIPS: microMIPS: Add vdso support. MIPS: microMIPS: Add unaligned access support. MIPS: microMIPS: Support handling of delay slots. MIPS: microMIPS: Add support for exception handling. MIPS: microMIPS: Floating point support. MIPS: microMIPS: Fix macro naming in micro-assembler. ...
Diffstat (limited to 'arch/mips/ralink')
-rw-r--r--arch/mips/ralink/Kconfig23
-rw-r--r--arch/mips/ralink/Makefile3
-rw-r--r--arch/mips/ralink/Platform18
-rw-r--r--arch/mips/ralink/common.h11
-rw-r--r--arch/mips/ralink/dts/Makefile3
-rw-r--r--arch/mips/ralink/dts/mt7620a.dtsi58
-rw-r--r--arch/mips/ralink/dts/mt7620a_eval.dts16
-rw-r--r--arch/mips/ralink/dts/rt2880.dtsi58
-rw-r--r--arch/mips/ralink/dts/rt2880_eval.dts46
-rw-r--r--arch/mips/ralink/dts/rt3050.dtsi52
-rw-r--r--arch/mips/ralink/dts/rt3052_eval.dts12
-rw-r--r--arch/mips/ralink/dts/rt3883.dtsi58
-rw-r--r--arch/mips/ralink/dts/rt3883_eval.dts16
-rw-r--r--arch/mips/ralink/early_printk.c4
-rw-r--r--arch/mips/ralink/irq.c5
-rw-r--r--arch/mips/ralink/mt7620.c234
-rw-r--r--arch/mips/ralink/of.c9
-rw-r--r--arch/mips/ralink/rt288x.c143
-rw-r--r--arch/mips/ralink/rt305x.c70
-rw-r--r--arch/mips/ralink/rt3883.c246
20 files changed, 1019 insertions, 66 deletions
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index a0b0197cab0a..026e823d871d 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -6,12 +6,23 @@ choice
6 help 6 help
7 Select Ralink MIPS SoC type. 7 Select Ralink MIPS SoC type.
8 8
9 config SOC_RT288X
10 bool "RT288x"
11
9 config SOC_RT305X 12 config SOC_RT305X
10 bool "RT305x" 13 bool "RT305x"
11 select USB_ARCH_HAS_HCD 14 select USB_ARCH_HAS_HCD
12 select USB_ARCH_HAS_OHCI 15 select USB_ARCH_HAS_OHCI
13 select USB_ARCH_HAS_EHCI 16 select USB_ARCH_HAS_EHCI
14 17
18 config SOC_RT3883
19 bool "RT3883"
20 select USB_ARCH_HAS_OHCI
21 select USB_ARCH_HAS_EHCI
22
23 config SOC_MT7620
24 bool "MT7620"
25
15endchoice 26endchoice
16 27
17choice 28choice
@@ -23,10 +34,22 @@ choice
23 config DTB_RT_NONE 34 config DTB_RT_NONE
24 bool "None" 35 bool "None"
25 36
37 config DTB_RT2880_EVAL
38 bool "RT2880 eval kit"
39 depends on SOC_RT288X
40
26 config DTB_RT305X_EVAL 41 config DTB_RT305X_EVAL
27 bool "RT305x eval kit" 42 bool "RT305x eval kit"
28 depends on SOC_RT305X 43 depends on SOC_RT305X
29 44
45 config DTB_RT3883_EVAL
46 bool "RT3883 eval kit"
47 depends on SOC_RT3883
48
49 config DTB_MT7620A_EVAL
50 bool "MT7620A eval kit"
51 depends on SOC_MT7620
52
30endchoice 53endchoice
31 54
32endif 55endif
diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
index 939757f0e71f..38cf1a880aaa 100644
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -8,7 +8,10 @@
8 8
9obj-y := prom.o of.o reset.o clk.o irq.o 9obj-y := prom.o of.o reset.o clk.o irq.o
10 10
11obj-$(CONFIG_SOC_RT288X) += rt288x.o
11obj-$(CONFIG_SOC_RT305X) += rt305x.o 12obj-$(CONFIG_SOC_RT305X) += rt305x.o
13obj-$(CONFIG_SOC_RT3883) += rt3883.o
14obj-$(CONFIG_SOC_MT7620) += mt7620.o
12 15
13obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 16obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
14 17
diff --git a/arch/mips/ralink/Platform b/arch/mips/ralink/Platform
index 6babd65765e6..cda4b6645c50 100644
--- a/arch/mips/ralink/Platform
+++ b/arch/mips/ralink/Platform
@@ -5,6 +5,24 @@ core-$(CONFIG_RALINK) += arch/mips/ralink/
5cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink 5cflags-$(CONFIG_RALINK) += -I$(srctree)/arch/mips/include/asm/mach-ralink
6 6
7# 7#
8# Ralink RT288x
9#
10load-$(CONFIG_SOC_RT288X) += 0xffffffff88000000
11cflags-$(CONFIG_SOC_RT288X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt288x
12
13#
8# Ralink RT305x 14# Ralink RT305x
9# 15#
10load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000 16load-$(CONFIG_SOC_RT305X) += 0xffffffff80000000
17cflags-$(CONFIG_SOC_RT305X) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt305x
18
19#
20# Ralink RT3883
21#
22load-$(CONFIG_SOC_RT3883) += 0xffffffff80000000
23cflags-$(CONFIG_SOC_RT3883) += -I$(srctree)/arch/mips/include/asm/mach-ralink/rt3883
24
25#
26# Ralink MT7620
27#
28load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
index 300990313e1b..83144c3fc5ac 100644
--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
@@ -22,13 +22,22 @@ struct ralink_pinmux {
22 struct ralink_pinmux_grp *mode; 22 struct ralink_pinmux_grp *mode;
23 struct ralink_pinmux_grp *uart; 23 struct ralink_pinmux_grp *uart;
24 int uart_shift; 24 int uart_shift;
25 u32 uart_mask;
25 void (*wdt_reset)(void); 26 void (*wdt_reset)(void);
27 struct ralink_pinmux_grp *pci;
28 int pci_shift;
29 u32 pci_mask;
26}; 30};
27extern struct ralink_pinmux gpio_pinmux; 31extern struct ralink_pinmux rt_gpio_pinmux;
28 32
29struct ralink_soc_info { 33struct ralink_soc_info {
30 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN]; 34 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
31 unsigned char *compatible; 35 unsigned char *compatible;
36
37 unsigned long mem_base;
38 unsigned long mem_size;
39 unsigned long mem_size_min;
40 unsigned long mem_size_max;
32}; 41};
33extern struct ralink_soc_info soc_info; 42extern struct ralink_soc_info soc_info;
34 43
diff --git a/arch/mips/ralink/dts/Makefile b/arch/mips/ralink/dts/Makefile
index 1a69fb300955..18194fa93e80 100644
--- a/arch/mips/ralink/dts/Makefile
+++ b/arch/mips/ralink/dts/Makefile
@@ -1 +1,4 @@
1obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
1obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o 2obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
3obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
4obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
diff --git a/arch/mips/ralink/dts/mt7620a.dtsi b/arch/mips/ralink/dts/mt7620a.dtsi
new file mode 100644
index 000000000000..08bf24fefe9f
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7620a.dtsi
@@ -0,0 +1,58 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,mtk7620a-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24KEc";
9 };
10 };
11
12 cpuintc: cpuintc@0 {
13 #address-cells = <0>;
14 #interrupt-cells = <1>;
15 interrupt-controller;
16 compatible = "mti,cpu-interrupt-controller";
17 };
18
19 palmbus@10000000 {
20 compatible = "palmbus";
21 reg = <0x10000000 0x200000>;
22 ranges = <0x0 0x10000000 0x1FFFFF>;
23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 sysc@0 {
28 compatible = "ralink,mt7620a-sysc";
29 reg = <0x0 0x100>;
30 };
31
32 intc: intc@200 {
33 compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
34 reg = <0x200 0x100>;
35
36 interrupt-controller;
37 #interrupt-cells = <1>;
38
39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>;
41 };
42
43 memc@300 {
44 compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
45 reg = <0x300 0x100>;
46 };
47
48 uartlite@c00 {
49 compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
50 reg = <0xc00 0x100>;
51
52 interrupt-parent = <&intc>;
53 interrupts = <12>;
54
55 reg-shift = <2>;
56 };
57 };
58};
diff --git a/arch/mips/ralink/dts/mt7620a_eval.dts b/arch/mips/ralink/dts/mt7620a_eval.dts
new file mode 100644
index 000000000000..35eb874ab7f1
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7620a_eval.dts
@@ -0,0 +1,16 @@
1/dts-v1/;
2
3/include/ "mt7620a.dtsi"
4
5/ {
6 compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
7 model = "Ralink MT7620A evaluation board";
8
9 memory@0 {
10 reg = <0x0 0x2000000>;
11 };
12
13 chosen {
14 bootargs = "console=ttyS0,57600";
15 };
16};
diff --git a/arch/mips/ralink/dts/rt2880.dtsi b/arch/mips/ralink/dts/rt2880.dtsi
new file mode 100644
index 000000000000..182afde2f2e1
--- /dev/null
+++ b/arch/mips/ralink/dts/rt2880.dtsi
@@ -0,0 +1,58 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,rt2880-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips4KEc";
9 };
10 };
11
12 cpuintc: cpuintc@0 {
13 #address-cells = <0>;
14 #interrupt-cells = <1>;
15 interrupt-controller;
16 compatible = "mti,cpu-interrupt-controller";
17 };
18
19 palmbus@300000 {
20 compatible = "palmbus";
21 reg = <0x300000 0x200000>;
22 ranges = <0x0 0x300000 0x1FFFFF>;
23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 sysc@0 {
28 compatible = "ralink,rt2880-sysc";
29 reg = <0x0 0x100>;
30 };
31
32 intc: intc@200 {
33 compatible = "ralink,rt2880-intc";
34 reg = <0x200 0x100>;
35
36 interrupt-controller;
37 #interrupt-cells = <1>;
38
39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>;
41 };
42
43 memc@300 {
44 compatible = "ralink,rt2880-memc";
45 reg = <0x300 0x100>;
46 };
47
48 uartlite@c00 {
49 compatible = "ralink,rt2880-uart", "ns16550a";
50 reg = <0xc00 0x100>;
51
52 interrupt-parent = <&intc>;
53 interrupts = <8>;
54
55 reg-shift = <2>;
56 };
57 };
58};
diff --git a/arch/mips/ralink/dts/rt2880_eval.dts b/arch/mips/ralink/dts/rt2880_eval.dts
new file mode 100644
index 000000000000..322d7002595b
--- /dev/null
+++ b/arch/mips/ralink/dts/rt2880_eval.dts
@@ -0,0 +1,46 @@
1/dts-v1/;
2
3/include/ "rt2880.dtsi"
4
5/ {
6 compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc";
7 model = "Ralink RT2880 evaluation board";
8
9 memory@0 {
10 reg = <0x8000000 0x2000000>;
11 };
12
13 chosen {
14 bootargs = "console=ttyS0,57600";
15 };
16
17 cfi@1f000000 {
18 compatible = "cfi-flash";
19 reg = <0x1f000000 0x400000>;
20
21 bank-width = <2>;
22 device-width = <2>;
23 #address-cells = <1>;
24 #size-cells = <1>;
25
26 partition@0 {
27 label = "uboot";
28 reg = <0x0 0x30000>;
29 read-only;
30 };
31 partition@30000 {
32 label = "uboot-env";
33 reg = <0x30000 0x10000>;
34 read-only;
35 };
36 partition@40000 {
37 label = "calibration";
38 reg = <0x40000 0x10000>;
39 read-only;
40 };
41 partition@50000 {
42 label = "linux";
43 reg = <0x50000 0x3b0000>;
44 };
45 };
46};
diff --git a/arch/mips/ralink/dts/rt3050.dtsi b/arch/mips/ralink/dts/rt3050.dtsi
index 069d0660e1dd..ef7da1e227e6 100644
--- a/arch/mips/ralink/dts/rt3050.dtsi
+++ b/arch/mips/ralink/dts/rt3050.dtsi
@@ -1,7 +1,7 @@
1/ { 1/ {
2 #address-cells = <1>; 2 #address-cells = <1>;
3 #size-cells = <1>; 3 #size-cells = <1>;
4 compatible = "ralink,rt3050-soc", "ralink,rt3052-soc"; 4 compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
5 5
6 cpus { 6 cpus {
7 cpu@0 { 7 cpu@0 {
@@ -9,10 +9,6 @@
9 }; 9 };
10 }; 10 };
11 11
12 chosen {
13 bootargs = "console=ttyS0,57600 init=/init";
14 };
15
16 cpuintc: cpuintc@0 { 12 cpuintc: cpuintc@0 {
17 #address-cells = <0>; 13 #address-cells = <0>;
18 #interrupt-cells = <1>; 14 #interrupt-cells = <1>;
@@ -23,7 +19,7 @@
23 palmbus@10000000 { 19 palmbus@10000000 {
24 compatible = "palmbus"; 20 compatible = "palmbus";
25 reg = <0x10000000 0x200000>; 21 reg = <0x10000000 0x200000>;
26 ranges = <0x0 0x10000000 0x1FFFFF>; 22 ranges = <0x0 0x10000000 0x1FFFFF>;
27 23
28 #address-cells = <1>; 24 #address-cells = <1>;
29 #size-cells = <1>; 25 #size-cells = <1>;
@@ -33,11 +29,6 @@
33 reg = <0x0 0x100>; 29 reg = <0x0 0x100>;
34 }; 30 };
35 31
36 timer@100 {
37 compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
38 reg = <0x100 0x100>;
39 };
40
41 intc: intc@200 { 32 intc: intc@200 {
42 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc"; 33 compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
43 reg = <0x200 0x100>; 34 reg = <0x200 0x100>;
@@ -54,45 +45,6 @@
54 reg = <0x300 0x100>; 45 reg = <0x300 0x100>;
55 }; 46 };
56 47
57 gpio0: gpio@600 {
58 compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
59 reg = <0x600 0x34>;
60
61 gpio-controller;
62 #gpio-cells = <2>;
63
64 ralink,ngpio = <24>;
65 ralink,regs = [ 00 04 08 0c
66 20 24 28 2c
67 30 34 ];
68 };
69
70 gpio1: gpio@638 {
71 compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
72 reg = <0x638 0x24>;
73
74 gpio-controller;
75 #gpio-cells = <2>;
76
77 ralink,ngpio = <16>;
78 ralink,regs = [ 00 04 08 0c
79 10 14 18 1c
80 20 24 ];
81 };
82
83 gpio2: gpio@660 {
84 compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
85 reg = <0x660 0x24>;
86
87 gpio-controller;
88 #gpio-cells = <2>;
89
90 ralink,ngpio = <12>;
91 ralink,regs = [ 00 04 08 0c
92 10 14 18 1c
93 20 24 ];
94 };
95
96 uartlite@c00 { 48 uartlite@c00 {
97 compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; 49 compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
98 reg = <0xc00 0x100>; 50 reg = <0xc00 0x100>;
diff --git a/arch/mips/ralink/dts/rt3052_eval.dts b/arch/mips/ralink/dts/rt3052_eval.dts
index 148a590bc419..c18c9a84f4c4 100644
--- a/arch/mips/ralink/dts/rt3052_eval.dts
+++ b/arch/mips/ralink/dts/rt3052_eval.dts
@@ -1,10 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "rt3050.dtsi" 3#include "rt3050.dtsi"
4 4
5/ { 5/ {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc"; 6 compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
9 model = "Ralink RT3052 evaluation board"; 7 model = "Ralink RT3052 evaluation board";
10 8
@@ -12,12 +10,8 @@
12 reg = <0x0 0x2000000>; 10 reg = <0x0 0x2000000>;
13 }; 11 };
14 12
15 palmbus@10000000 { 13 chosen {
16 sysc@0 { 14 bootargs = "console=ttyS0,57600";
17 ralink,pinmmux = "uartlite", "spi";
18 ralink,uartmux = "gpio";
19 ralink,wdtmux = <0>;
20 };
21 }; 15 };
22 16
23 cfi@1f000000 { 17 cfi@1f000000 {
diff --git a/arch/mips/ralink/dts/rt3883.dtsi b/arch/mips/ralink/dts/rt3883.dtsi
new file mode 100644
index 000000000000..3b131dd0d5ac
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3883.dtsi
@@ -0,0 +1,58 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,rt3883-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips74Kc";
9 };
10 };
11
12 cpuintc: cpuintc@0 {
13 #address-cells = <0>;
14 #interrupt-cells = <1>;
15 interrupt-controller;
16 compatible = "mti,cpu-interrupt-controller";
17 };
18
19 palmbus@10000000 {
20 compatible = "palmbus";
21 reg = <0x10000000 0x200000>;
22 ranges = <0x0 0x10000000 0x1FFFFF>;
23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 sysc@0 {
28 compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
29 reg = <0x0 0x100>;
30 };
31
32 intc: intc@200 {
33 compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
34 reg = <0x200 0x100>;
35
36 interrupt-controller;
37 #interrupt-cells = <1>;
38
39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>;
41 };
42
43 memc@300 {
44 compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
45 reg = <0x300 0x100>;
46 };
47
48 uartlite@c00 {
49 compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
50 reg = <0xc00 0x100>;
51
52 interrupt-parent = <&intc>;
53 interrupts = <12>;
54
55 reg-shift = <2>;
56 };
57 };
58};
diff --git a/arch/mips/ralink/dts/rt3883_eval.dts b/arch/mips/ralink/dts/rt3883_eval.dts
new file mode 100644
index 000000000000..2fa6b330bf4f
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3883_eval.dts
@@ -0,0 +1,16 @@
1/dts-v1/;
2
3/include/ "rt3883.dtsi"
4
5/ {
6 compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc";
7 model = "Ralink RT3883 evaluation board";
8
9 memory@0 {
10 reg = <0x0 0x2000000>;
11 };
12
13 chosen {
14 bootargs = "console=ttyS0,57600";
15 };
16};
diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c
index c4ae47eb24ab..b46d0419d09b 100644
--- a/arch/mips/ralink/early_printk.c
+++ b/arch/mips/ralink/early_printk.c
@@ -11,7 +11,11 @@
11 11
12#include <asm/addrspace.h> 12#include <asm/addrspace.h>
13 13
14#ifdef CONFIG_SOC_RT288X
15#define EARLY_UART_BASE 0x300c00
16#else
14#define EARLY_UART_BASE 0x10000c00 17#define EARLY_UART_BASE 0x10000c00
18#endif
15 19
16#define UART_REG_RX 0x00 20#define UART_REG_RX 0x00
17#define UART_REG_TX 0x04 21#define UART_REG_TX 0x04
diff --git a/arch/mips/ralink/irq.c b/arch/mips/ralink/irq.c
index 6d054c5ec9ab..320b1f1043ff 100644
--- a/arch/mips/ralink/irq.c
+++ b/arch/mips/ralink/irq.c
@@ -31,6 +31,7 @@
31#define INTC_INT_GLOBAL BIT(31) 31#define INTC_INT_GLOBAL BIT(31)
32 32
33#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2) 33#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
34#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
34#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5) 35#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
35#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6) 36#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
36#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7) 37#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
@@ -104,6 +105,9 @@ asmlinkage void plat_irq_dispatch(void)
104 else if (pending & STATUSF_IP6) 105 else if (pending & STATUSF_IP6)
105 do_IRQ(RALINK_CPU_IRQ_WIFI); 106 do_IRQ(RALINK_CPU_IRQ_WIFI);
106 107
108 else if (pending & STATUSF_IP4)
109 do_IRQ(RALINK_CPU_IRQ_PCI);
110
107 else if (pending & STATUSF_IP2) 111 else if (pending & STATUSF_IP2)
108 do_IRQ(RALINK_CPU_IRQ_INTC); 112 do_IRQ(RALINK_CPU_IRQ_INTC);
109 113
@@ -162,6 +166,7 @@ static int __init intc_of_init(struct device_node *node,
162 irq_set_chained_handler(irq, ralink_intc_irq_handler); 166 irq_set_chained_handler(irq, ralink_intc_irq_handler);
163 irq_set_handler_data(irq, domain); 167 irq_set_handler_data(irq, domain);
164 168
169 /* tell the kernel which irq is used for performance monitoring */
165 cp0_perfcount_irq = irq_create_mapping(domain, 9); 170 cp0_perfcount_irq = irq_create_mapping(domain, 9);
166 171
167 return 0; 172 return 0;
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
new file mode 100644
index 000000000000..0018b1a661f6
--- /dev/null
+++ b/arch/mips/ralink/mt7620.c
@@ -0,0 +1,234 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/mt7620.h>
20
21#include "common.h"
22
23/* does the board have sdram or ddram */
24static int dram_type;
25
26/* the pll dividers */
27static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
28
29static struct ralink_pinmux_grp mode_mux[] = {
30 {
31 .name = "i2c",
32 .mask = MT7620_GPIO_MODE_I2C,
33 .gpio_first = 1,
34 .gpio_last = 2,
35 }, {
36 .name = "spi",
37 .mask = MT7620_GPIO_MODE_SPI,
38 .gpio_first = 3,
39 .gpio_last = 6,
40 }, {
41 .name = "uartlite",
42 .mask = MT7620_GPIO_MODE_UART1,
43 .gpio_first = 15,
44 .gpio_last = 16,
45 }, {
46 .name = "wdt",
47 .mask = MT7620_GPIO_MODE_WDT,
48 .gpio_first = 17,
49 .gpio_last = 17,
50 }, {
51 .name = "mdio",
52 .mask = MT7620_GPIO_MODE_MDIO,
53 .gpio_first = 22,
54 .gpio_last = 23,
55 }, {
56 .name = "rgmii1",
57 .mask = MT7620_GPIO_MODE_RGMII1,
58 .gpio_first = 24,
59 .gpio_last = 35,
60 }, {
61 .name = "spi refclk",
62 .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
63 .gpio_first = 37,
64 .gpio_last = 39,
65 }, {
66 .name = "jtag",
67 .mask = MT7620_GPIO_MODE_JTAG,
68 .gpio_first = 40,
69 .gpio_last = 44,
70 }, {
71 /* shared lines with jtag */
72 .name = "ephy",
73 .mask = MT7620_GPIO_MODE_EPHY,
74 .gpio_first = 40,
75 .gpio_last = 44,
76 }, {
77 .name = "nand",
78 .mask = MT7620_GPIO_MODE_JTAG,
79 .gpio_first = 45,
80 .gpio_last = 59,
81 }, {
82 .name = "rgmii2",
83 .mask = MT7620_GPIO_MODE_RGMII2,
84 .gpio_first = 60,
85 .gpio_last = 71,
86 }, {
87 .name = "wled",
88 .mask = MT7620_GPIO_MODE_WLED,
89 .gpio_first = 72,
90 .gpio_last = 72,
91 }, {0}
92};
93
94static struct ralink_pinmux_grp uart_mux[] = {
95 {
96 .name = "uartf",
97 .mask = MT7620_GPIO_MODE_UARTF,
98 .gpio_first = 7,
99 .gpio_last = 14,
100 }, {
101 .name = "pcm uartf",
102 .mask = MT7620_GPIO_MODE_PCM_UARTF,
103 .gpio_first = 7,
104 .gpio_last = 14,
105 }, {
106 .name = "pcm i2s",
107 .mask = MT7620_GPIO_MODE_PCM_I2S,
108 .gpio_first = 7,
109 .gpio_last = 14,
110 }, {
111 .name = "i2s uartf",
112 .mask = MT7620_GPIO_MODE_I2S_UARTF,
113 .gpio_first = 7,
114 .gpio_last = 14,
115 }, {
116 .name = "pcm gpio",
117 .mask = MT7620_GPIO_MODE_PCM_GPIO,
118 .gpio_first = 11,
119 .gpio_last = 14,
120 }, {
121 .name = "gpio uartf",
122 .mask = MT7620_GPIO_MODE_GPIO_UARTF,
123 .gpio_first = 7,
124 .gpio_last = 10,
125 }, {
126 .name = "gpio i2s",
127 .mask = MT7620_GPIO_MODE_GPIO_I2S,
128 .gpio_first = 7,
129 .gpio_last = 10,
130 }, {
131 .name = "gpio",
132 .mask = MT7620_GPIO_MODE_GPIO,
133 }, {0}
134};
135
136struct ralink_pinmux rt_gpio_pinmux = {
137 .mode = mode_mux,
138 .uart = uart_mux,
139 .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
140 .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
141};
142
143void __init ralink_clk_init(void)
144{
145 unsigned long cpu_rate, sys_rate;
146 u32 c0 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
147 u32 c1 = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
148 u32 swconfig = (c0 >> CPLL_SW_CONFIG_SHIFT) & CPLL_SW_CONFIG_MASK;
149 u32 cpu_clk = (c1 >> CPLL_CPU_CLK_SHIFT) & CPLL_CPU_CLK_MASK;
150
151 if (cpu_clk) {
152 cpu_rate = 480000000;
153 } else if (!swconfig) {
154 cpu_rate = 600000000;
155 } else {
156 u32 m = (c0 >> CPLL_MULT_RATIO_SHIFT) & CPLL_MULT_RATIO;
157 u32 d = (c0 >> CPLL_DIV_RATIO_SHIFT) & CPLL_DIV_RATIO;
158
159 cpu_rate = ((40 * (m + 24)) / mt7620_clk_divider[d]) * 1000000;
160 }
161
162 if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
163 sys_rate = cpu_rate / 4;
164 else
165 sys_rate = cpu_rate / 3;
166
167 ralink_clk_add("cpu", cpu_rate);
168 ralink_clk_add("10000100.timer", 40000000);
169 ralink_clk_add("10000500.uart", 40000000);
170 ralink_clk_add("10000c00.uartlite", 40000000);
171}
172
173void __init ralink_of_remap(void)
174{
175 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
176 rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
177
178 if (!rt_sysc_membase || !rt_memc_membase)
179 panic("Failed to remap core resources");
180}
181
182void prom_soc_init(struct ralink_soc_info *soc_info)
183{
184 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
185 unsigned char *name = NULL;
186 u32 n0;
187 u32 n1;
188 u32 rev;
189 u32 cfg0;
190
191 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
192 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
193
194 if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
195 name = "MT7620N";
196 soc_info->compatible = "ralink,mt7620n-soc";
197 } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
198 name = "MT7620A";
199 soc_info->compatible = "ralink,mt7620a-soc";
200 } else {
201 panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
202 }
203
204 rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
205
206 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
207 "Ralink %s ver:%u eco:%u",
208 name,
209 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
210 (rev & CHIP_REV_ECO_MASK));
211
212 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
213 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
214
215 switch (dram_type) {
216 case SYSCFG0_DRAM_TYPE_SDRAM:
217 soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
218 soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
219 break;
220
221 case SYSCFG0_DRAM_TYPE_DDR1:
222 soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
223 soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
224 break;
225
226 case SYSCFG0_DRAM_TYPE_DDR2:
227 soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
228 soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
229 break;
230 default:
231 BUG();
232 }
233 soc_info->mem_base = MT7620_DRAM_BASE;
234}
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
index 4165e70775be..fb1569580def 100644
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -11,6 +11,7 @@
11#include <linux/io.h> 11#include <linux/io.h>
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/sizes.h>
14#include <linux/of_fdt.h> 15#include <linux/of_fdt.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/bootmem.h> 17#include <linux/bootmem.h>
@@ -85,6 +86,14 @@ void __init plat_mem_setup(void)
85 * parsed resulting in our memory appearing 86 * parsed resulting in our memory appearing
86 */ 87 */
87 __dt_setup_arch(&__dtb_start); 88 __dt_setup_arch(&__dtb_start);
89
90 if (soc_info.mem_size)
91 add_memory_region(soc_info.mem_base, soc_info.mem_size,
92 BOOT_MEM_RAM);
93 else
94 detect_memory_region(soc_info.mem_base,
95 soc_info.mem_size_min * SZ_1M,
96 soc_info.mem_size_max * SZ_1M);
88} 97}
89 98
90static int __init plat_of_setup(void) 99static int __init plat_of_setup(void)
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
new file mode 100644
index 000000000000..f87de1ab2198
--- /dev/null
+++ b/arch/mips/ralink/rt288x.c
@@ -0,0 +1,143 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt288x.h>
20
21#include "common.h"
22
23static struct ralink_pinmux_grp mode_mux[] = {
24 {
25 .name = "i2c",
26 .mask = RT2880_GPIO_MODE_I2C,
27 .gpio_first = 1,
28 .gpio_last = 2,
29 }, {
30 .name = "spi",
31 .mask = RT2880_GPIO_MODE_SPI,
32 .gpio_first = 3,
33 .gpio_last = 6,
34 }, {
35 .name = "uartlite",
36 .mask = RT2880_GPIO_MODE_UART0,
37 .gpio_first = 7,
38 .gpio_last = 14,
39 }, {
40 .name = "jtag",
41 .mask = RT2880_GPIO_MODE_JTAG,
42 .gpio_first = 17,
43 .gpio_last = 21,
44 }, {
45 .name = "mdio",
46 .mask = RT2880_GPIO_MODE_MDIO,
47 .gpio_first = 22,
48 .gpio_last = 23,
49 }, {
50 .name = "sdram",
51 .mask = RT2880_GPIO_MODE_SDRAM,
52 .gpio_first = 24,
53 .gpio_last = 39,
54 }, {
55 .name = "pci",
56 .mask = RT2880_GPIO_MODE_PCI,
57 .gpio_first = 40,
58 .gpio_last = 71,
59 }, {0}
60};
61
62static void rt288x_wdt_reset(void)
63{
64 u32 t;
65
66 /* enable WDT reset output on pin SRAM_CS_N */
67 t = rt_sysc_r32(SYSC_REG_CLKCFG);
68 t |= CLKCFG_SRAM_CS_N_WDT;
69 rt_sysc_w32(t, SYSC_REG_CLKCFG);
70}
71
72struct ralink_pinmux rt_gpio_pinmux = {
73 .mode = mode_mux,
74 .wdt_reset = rt288x_wdt_reset,
75};
76
77void __init ralink_clk_init(void)
78{
79 unsigned long cpu_rate;
80 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
81 t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
82
83 switch (t) {
84 case SYSTEM_CONFIG_CPUCLK_250:
85 cpu_rate = 250000000;
86 break;
87 case SYSTEM_CONFIG_CPUCLK_266:
88 cpu_rate = 266666667;
89 break;
90 case SYSTEM_CONFIG_CPUCLK_280:
91 cpu_rate = 280000000;
92 break;
93 case SYSTEM_CONFIG_CPUCLK_300:
94 cpu_rate = 300000000;
95 break;
96 }
97
98 ralink_clk_add("cpu", cpu_rate);
99 ralink_clk_add("300100.timer", cpu_rate / 2);
100 ralink_clk_add("300120.watchdog", cpu_rate / 2);
101 ralink_clk_add("300500.uart", cpu_rate / 2);
102 ralink_clk_add("300c00.uartlite", cpu_rate / 2);
103 ralink_clk_add("400000.ethernet", cpu_rate / 2);
104}
105
106void __init ralink_of_remap(void)
107{
108 rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
109 rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
110
111 if (!rt_sysc_membase || !rt_memc_membase)
112 panic("Failed to remap core resources");
113}
114
115void prom_soc_init(struct ralink_soc_info *soc_info)
116{
117 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
118 const char *name;
119 u32 n0;
120 u32 n1;
121 u32 id;
122
123 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
124 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
125 id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
126
127 if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
128 soc_info->compatible = "ralink,r2880-soc";
129 name = "RT2880";
130 } else {
131 panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
132 }
133
134 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
135 "Ralink %s id:%u rev:%u",
136 name,
137 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
138 (id & CHIP_ID_REV_MASK));
139
140 soc_info->mem_base = RT2880_SDRAM_BASE;
141 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
142 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
143}
diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
index 0a4bbdcf59d9..ca7ee3a33790 100644
--- a/arch/mips/ralink/rt305x.c
+++ b/arch/mips/ralink/rt305x.c
@@ -22,7 +22,7 @@
22 22
23enum rt305x_soc_type rt305x_soc; 23enum rt305x_soc_type rt305x_soc;
24 24
25struct ralink_pinmux_grp mode_mux[] = { 25static struct ralink_pinmux_grp mode_mux[] = {
26 { 26 {
27 .name = "i2c", 27 .name = "i2c",
28 .mask = RT305X_GPIO_MODE_I2C, 28 .mask = RT305X_GPIO_MODE_I2C,
@@ -61,7 +61,7 @@ struct ralink_pinmux_grp mode_mux[] = {
61 }, {0} 61 }, {0}
62}; 62};
63 63
64struct ralink_pinmux_grp uart_mux[] = { 64static struct ralink_pinmux_grp uart_mux[] = {
65 { 65 {
66 .name = "uartf", 66 .name = "uartf",
67 .mask = RT305X_GPIO_MODE_UARTF, 67 .mask = RT305X_GPIO_MODE_UARTF,
@@ -91,19 +91,19 @@ struct ralink_pinmux_grp uart_mux[] = {
91 .name = "gpio uartf", 91 .name = "gpio uartf",
92 .mask = RT305X_GPIO_MODE_GPIO_UARTF, 92 .mask = RT305X_GPIO_MODE_GPIO_UARTF,
93 .gpio_first = RT305X_GPIO_7, 93 .gpio_first = RT305X_GPIO_7,
94 .gpio_last = RT305X_GPIO_14, 94 .gpio_last = RT305X_GPIO_10,
95 }, { 95 }, {
96 .name = "gpio i2s", 96 .name = "gpio i2s",
97 .mask = RT305X_GPIO_MODE_GPIO_I2S, 97 .mask = RT305X_GPIO_MODE_GPIO_I2S,
98 .gpio_first = RT305X_GPIO_7, 98 .gpio_first = RT305X_GPIO_7,
99 .gpio_last = RT305X_GPIO_14, 99 .gpio_last = RT305X_GPIO_10,
100 }, { 100 }, {
101 .name = "gpio", 101 .name = "gpio",
102 .mask = RT305X_GPIO_MODE_GPIO, 102 .mask = RT305X_GPIO_MODE_GPIO,
103 }, {0} 103 }, {0}
104}; 104};
105 105
106void rt305x_wdt_reset(void) 106static void rt305x_wdt_reset(void)
107{ 107{
108 u32 t; 108 u32 t;
109 109
@@ -114,16 +114,53 @@ void rt305x_wdt_reset(void)
114 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); 114 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
115} 115}
116 116
117struct ralink_pinmux gpio_pinmux = { 117struct ralink_pinmux rt_gpio_pinmux = {
118 .mode = mode_mux, 118 .mode = mode_mux,
119 .uart = uart_mux, 119 .uart = uart_mux,
120 .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT, 120 .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
121 .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
121 .wdt_reset = rt305x_wdt_reset, 122 .wdt_reset = rt305x_wdt_reset,
122}; 123};
123 124
125static unsigned long rt5350_get_mem_size(void)
126{
127 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
128 unsigned long ret;
129 u32 t;
130
131 t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
132 t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
133 RT5350_SYSCFG0_DRAM_SIZE_MASK;
134
135 switch (t) {
136 case RT5350_SYSCFG0_DRAM_SIZE_2M:
137 ret = 2;
138 break;
139 case RT5350_SYSCFG0_DRAM_SIZE_8M:
140 ret = 8;
141 break;
142 case RT5350_SYSCFG0_DRAM_SIZE_16M:
143 ret = 16;
144 break;
145 case RT5350_SYSCFG0_DRAM_SIZE_32M:
146 ret = 32;
147 break;
148 case RT5350_SYSCFG0_DRAM_SIZE_64M:
149 ret = 64;
150 break;
151 default:
152 panic("rt5350: invalid DRAM size: %u", t);
153 break;
154 }
155
156 return ret;
157}
158
124void __init ralink_clk_init(void) 159void __init ralink_clk_init(void)
125{ 160{
126 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; 161 unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
162 unsigned long wmac_rate = 40000000;
163
127 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); 164 u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
128 165
129 if (soc_is_rt305x() || soc_is_rt3350()) { 166 if (soc_is_rt305x() || soc_is_rt3350()) {
@@ -176,11 +213,21 @@ void __init ralink_clk_init(void)
176 BUG(); 213 BUG();
177 } 214 }
178 215
216 if (soc_is_rt3352() || soc_is_rt5350()) {
217 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
218
219 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
220 wmac_rate = 20000000;
221 }
222
179 ralink_clk_add("cpu", cpu_rate); 223 ralink_clk_add("cpu", cpu_rate);
180 ralink_clk_add("10000b00.spi", sys_rate); 224 ralink_clk_add("10000b00.spi", sys_rate);
181 ralink_clk_add("10000100.timer", wdt_rate); 225 ralink_clk_add("10000100.timer", wdt_rate);
226 ralink_clk_add("10000120.watchdog", wdt_rate);
182 ralink_clk_add("10000500.uart", uart_rate); 227 ralink_clk_add("10000500.uart", uart_rate);
183 ralink_clk_add("10000c00.uartlite", uart_rate); 228 ralink_clk_add("10000c00.uartlite", uart_rate);
229 ralink_clk_add("10100000.ethernet", sys_rate);
230 ralink_clk_add("10180000.wmac", wmac_rate);
184} 231}
185 232
186void __init ralink_of_remap(void) 233void __init ralink_of_remap(void)
@@ -239,4 +286,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
239 name, 286 name,
240 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK, 287 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
241 (id & CHIP_ID_REV_MASK)); 288 (id & CHIP_ID_REV_MASK));
289
290 soc_info->mem_base = RT305X_SDRAM_BASE;
291 if (soc_is_rt5350()) {
292 soc_info->mem_size = rt5350_get_mem_size();
293 } else if (soc_is_rt305x() || soc_is_rt3350()) {
294 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
295 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
296 } else if (soc_is_rt3352()) {
297 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
298 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
299 }
242} 300}
diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c
new file mode 100644
index 000000000000..b474ac284b83
--- /dev/null
+++ b/arch/mips/ralink/rt3883.c
@@ -0,0 +1,246 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/module.h>
16
17#include <asm/mipsregs.h>
18#include <asm/mach-ralink/ralink_regs.h>
19#include <asm/mach-ralink/rt3883.h>
20
21#include "common.h"
22
23static struct ralink_pinmux_grp mode_mux[] = {
24 {
25 .name = "i2c",
26 .mask = RT3883_GPIO_MODE_I2C,
27 .gpio_first = RT3883_GPIO_I2C_SD,
28 .gpio_last = RT3883_GPIO_I2C_SCLK,
29 }, {
30 .name = "spi",
31 .mask = RT3883_GPIO_MODE_SPI,
32 .gpio_first = RT3883_GPIO_SPI_CS0,
33 .gpio_last = RT3883_GPIO_SPI_MISO,
34 }, {
35 .name = "uartlite",
36 .mask = RT3883_GPIO_MODE_UART1,
37 .gpio_first = RT3883_GPIO_UART1_TXD,
38 .gpio_last = RT3883_GPIO_UART1_RXD,
39 }, {
40 .name = "jtag",
41 .mask = RT3883_GPIO_MODE_JTAG,
42 .gpio_first = RT3883_GPIO_JTAG_TDO,
43 .gpio_last = RT3883_GPIO_JTAG_TCLK,
44 }, {
45 .name = "mdio",
46 .mask = RT3883_GPIO_MODE_MDIO,
47 .gpio_first = RT3883_GPIO_MDIO_MDC,
48 .gpio_last = RT3883_GPIO_MDIO_MDIO,
49 }, {
50 .name = "ge1",
51 .mask = RT3883_GPIO_MODE_GE1,
52 .gpio_first = RT3883_GPIO_GE1_TXD0,
53 .gpio_last = RT3883_GPIO_GE1_RXCLK,
54 }, {
55 .name = "ge2",
56 .mask = RT3883_GPIO_MODE_GE2,
57 .gpio_first = RT3883_GPIO_GE2_TXD0,
58 .gpio_last = RT3883_GPIO_GE2_RXCLK,
59 }, {
60 .name = "pci",
61 .mask = RT3883_GPIO_MODE_PCI,
62 .gpio_first = RT3883_GPIO_PCI_AD0,
63 .gpio_last = RT3883_GPIO_PCI_AD31,
64 }, {
65 .name = "lna a",
66 .mask = RT3883_GPIO_MODE_LNA_A,
67 .gpio_first = RT3883_GPIO_LNA_PE_A0,
68 .gpio_last = RT3883_GPIO_LNA_PE_A2,
69 }, {
70 .name = "lna g",
71 .mask = RT3883_GPIO_MODE_LNA_G,
72 .gpio_first = RT3883_GPIO_LNA_PE_G0,
73 .gpio_last = RT3883_GPIO_LNA_PE_G2,
74 }, {0}
75};
76
77static struct ralink_pinmux_grp uart_mux[] = {
78 {
79 .name = "uartf",
80 .mask = RT3883_GPIO_MODE_UARTF,
81 .gpio_first = RT3883_GPIO_7,
82 .gpio_last = RT3883_GPIO_14,
83 }, {
84 .name = "pcm uartf",
85 .mask = RT3883_GPIO_MODE_PCM_UARTF,
86 .gpio_first = RT3883_GPIO_7,
87 .gpio_last = RT3883_GPIO_14,
88 }, {
89 .name = "pcm i2s",
90 .mask = RT3883_GPIO_MODE_PCM_I2S,
91 .gpio_first = RT3883_GPIO_7,
92 .gpio_last = RT3883_GPIO_14,
93 }, {
94 .name = "i2s uartf",
95 .mask = RT3883_GPIO_MODE_I2S_UARTF,
96 .gpio_first = RT3883_GPIO_7,
97 .gpio_last = RT3883_GPIO_14,
98 }, {
99 .name = "pcm gpio",
100 .mask = RT3883_GPIO_MODE_PCM_GPIO,
101 .gpio_first = RT3883_GPIO_11,
102 .gpio_last = RT3883_GPIO_14,
103 }, {
104 .name = "gpio uartf",
105 .mask = RT3883_GPIO_MODE_GPIO_UARTF,
106 .gpio_first = RT3883_GPIO_7,
107 .gpio_last = RT3883_GPIO_10,
108 }, {
109 .name = "gpio i2s",
110 .mask = RT3883_GPIO_MODE_GPIO_I2S,
111 .gpio_first = RT3883_GPIO_7,
112 .gpio_last = RT3883_GPIO_10,
113 }, {
114 .name = "gpio",
115 .mask = RT3883_GPIO_MODE_GPIO,
116 }, {0}
117};
118
119static struct ralink_pinmux_grp pci_mux[] = {
120 {
121 .name = "pci-dev",
122 .mask = 0,
123 .gpio_first = RT3883_GPIO_PCI_AD0,
124 .gpio_last = RT3883_GPIO_PCI_AD31,
125 }, {
126 .name = "pci-host2",
127 .mask = 1,
128 .gpio_first = RT3883_GPIO_PCI_AD0,
129 .gpio_last = RT3883_GPIO_PCI_AD31,
130 }, {
131 .name = "pci-host1",
132 .mask = 2,
133 .gpio_first = RT3883_GPIO_PCI_AD0,
134 .gpio_last = RT3883_GPIO_PCI_AD31,
135 }, {
136 .name = "pci-fnc",
137 .mask = 3,
138 .gpio_first = RT3883_GPIO_PCI_AD0,
139 .gpio_last = RT3883_GPIO_PCI_AD31,
140 }, {
141 .name = "pci-gpio",
142 .mask = 7,
143 .gpio_first = RT3883_GPIO_PCI_AD0,
144 .gpio_last = RT3883_GPIO_PCI_AD31,
145 }, {0}
146};
147
148static void rt3883_wdt_reset(void)
149{
150 u32 t;
151
152 /* enable WDT reset output on GPIO 2 */
153 t = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
154 t |= RT3883_SYSCFG1_GPIO2_AS_WDT_OUT;
155 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
156}
157
158struct ralink_pinmux rt_gpio_pinmux = {
159 .mode = mode_mux,
160 .uart = uart_mux,
161 .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
162 .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
163 .wdt_reset = rt3883_wdt_reset,
164 .pci = pci_mux,
165 .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
166 .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
167};
168
169void __init ralink_clk_init(void)
170{
171 unsigned long cpu_rate, sys_rate;
172 u32 syscfg0;
173 u32 clksel;
174 u32 ddr2;
175
176 syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
177 clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
178 RT3883_SYSCFG0_CPUCLK_MASK);
179 ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
180
181 switch (clksel) {
182 case RT3883_SYSCFG0_CPUCLK_250:
183 cpu_rate = 250000000;
184 sys_rate = (ddr2) ? 125000000 : 83000000;
185 break;
186 case RT3883_SYSCFG0_CPUCLK_384:
187 cpu_rate = 384000000;
188 sys_rate = (ddr2) ? 128000000 : 96000000;
189 break;
190 case RT3883_SYSCFG0_CPUCLK_480:
191 cpu_rate = 480000000;
192 sys_rate = (ddr2) ? 160000000 : 120000000;
193 break;
194 case RT3883_SYSCFG0_CPUCLK_500:
195 cpu_rate = 500000000;
196 sys_rate = (ddr2) ? 166000000 : 125000000;
197 break;
198 }
199
200 ralink_clk_add("cpu", cpu_rate);
201 ralink_clk_add("10000100.timer", sys_rate);
202 ralink_clk_add("10000120.watchdog", sys_rate);
203 ralink_clk_add("10000500.uart", 40000000);
204 ralink_clk_add("10000b00.spi", sys_rate);
205 ralink_clk_add("10000c00.uartlite", 40000000);
206 ralink_clk_add("10100000.ethernet", sys_rate);
207}
208
209void __init ralink_of_remap(void)
210{
211 rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
212 rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
213
214 if (!rt_sysc_membase || !rt_memc_membase)
215 panic("Failed to remap core resources");
216}
217
218void prom_soc_init(struct ralink_soc_info *soc_info)
219{
220 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
221 const char *name;
222 u32 n0;
223 u32 n1;
224 u32 id;
225
226 n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
227 n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
228 id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
229
230 if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
231 soc_info->compatible = "ralink,rt3883-soc";
232 name = "RT3883";
233 } else {
234 panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
235 }
236
237 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
238 "Ralink %s ver:%u eco:%u",
239 name,
240 (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
241 (id & RT3883_REVID_ECO_ID_MASK));
242
243 soc_info->mem_base = RT3883_SDRAM_BASE;
244 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
245 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
246}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 15:32:55 -0500