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authorJohn Crispin <blogic@openwrt.org>2013-04-12 02:27:39 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-05-07 19:19:11 -0400
commit6fbfe90e58b03c4126e3f21d9d9cc53c116003b2 (patch)
tree25f2ff741ee4795cf539fa25956201b8641ddc54 /arch/mips/ralink/dts/rt3883.dtsi
parentd99e19c799a6b48a5c6d733f5885862df5c77c70 (diff)
DT: MIPS: ralink: add RT3883 dts files
Add a dtsi file for RT3883 SoC and a sample dts file. Signed-off-by: John Crispin <blogic@openwrt.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Patchwork: http://patchwork.linux-mips.org/patch/5189/
Diffstat (limited to 'arch/mips/ralink/dts/rt3883.dtsi')
-rw-r--r--arch/mips/ralink/dts/rt3883.dtsi58
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/mips/ralink/dts/rt3883.dtsi b/arch/mips/ralink/dts/rt3883.dtsi
new file mode 100644
index 000000000000..3b131dd0d5ac
--- /dev/null
+++ b/arch/mips/ralink/dts/rt3883.dtsi
@@ -0,0 +1,58 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "ralink,rt3883-soc";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips74Kc";
9 };
10 };
11
12 cpuintc: cpuintc@0 {
13 #address-cells = <0>;
14 #interrupt-cells = <1>;
15 interrupt-controller;
16 compatible = "mti,cpu-interrupt-controller";
17 };
18
19 palmbus@10000000 {
20 compatible = "palmbus";
21 reg = <0x10000000 0x200000>;
22 ranges = <0x0 0x10000000 0x1FFFFF>;
23
24 #address-cells = <1>;
25 #size-cells = <1>;
26
27 sysc@0 {
28 compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc";
29 reg = <0x0 0x100>;
30 };
31
32 intc: intc@200 {
33 compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
34 reg = <0x200 0x100>;
35
36 interrupt-controller;
37 #interrupt-cells = <1>;
38
39 interrupt-parent = <&cpuintc>;
40 interrupts = <2>;
41 };
42
43 memc@300 {
44 compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
45 reg = <0x300 0x100>;
46 };
47
48 uartlite@c00 {
49 compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
50 reg = <0xc00 0x100>;
51
52 interrupt-parent = <&intc>;
53 interrupts = <12>;
54
55 reg-shift = <2>;
56 };
57 };
58};