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authorDavid VomLehn <dvomlehn@cisco.com>2009-12-23 20:34:46 -0500
committerRalf Baechle <ralf@linux-mips.org>2010-01-27 18:03:31 -0500
commit59dfa2fcaecc39fb88bfa196cb15adca7146867a (patch)
tree25a1e3541ec399110d7a53ac8162e1bbcbd5efc0 /arch/mips/powertv/asic/asic-calliope.c
parent9c4a6fce2032fcb5bb8339d53fd3dadfd7ddfb98 (diff)
MIPS: PowerTV: Streamline access to platform device registers
Pre-compute addresses for the basic ASIC registers. This speeds up access and allows memory for unused configurations to be freed. In addition, uninitialized register addresses will be returned as NULL to catch bad usage quickly. Signed-off-by: David VomLehn <dvomlehn@cisco.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/806/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/powertv/asic/asic-calliope.c')
-rw-r--r--arch/mips/powertv/asic/asic-calliope.c131
1 files changed, 67 insertions, 64 deletions
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 03d3884c6270..1ae6623444b2 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -23,76 +23,79 @@
23 * Description: Defines the platform resources for the SA settop. 23 * Description: Defines the platform resources for the SA settop.
24 */ 24 */
25 25
26#include <linux/init.h>
26#include <asm/mach-powertv/asic.h> 27#include <asm/mach-powertv/asic.h>
27 28
28const struct register_map calliope_register_map = { 29#define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x))
29 .eic_slow0_strt_add = 0x800000,
30 .eic_cfg_bits = 0x800038,
31 .eic_ready_status = 0x80004c,
32 30
33 .chipver3 = 0xA00800, 31const struct register_map calliope_register_map __initdata = {
34 .chipver2 = 0xA00804, 32 .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
35 .chipver1 = 0xA00808, 33 .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
36 .chipver0 = 0xA0080c, 34 .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
35
36 .chipver3 = {.phys = CALLIOPE_ADDR(0xA00800)},
37 .chipver2 = {.phys = CALLIOPE_ADDR(0xA00804)},
38 .chipver1 = {.phys = CALLIOPE_ADDR(0xA00808)},
39 .chipver0 = {.phys = CALLIOPE_ADDR(0xA0080c)},
37 40
38 /* The registers of IRBlaster */ 41 /* The registers of IRBlaster */
39 .uart1_intstat = 0xA01800, 42 .uart1_intstat = {.phys = CALLIOPE_ADDR(0xA01800)},
40 .uart1_inten = 0xA01804, 43 .uart1_inten = {.phys = CALLIOPE_ADDR(0xA01804)},
41 .uart1_config1 = 0xA01808, 44 .uart1_config1 = {.phys = CALLIOPE_ADDR(0xA01808)},
42 .uart1_config2 = 0xA0180C, 45 .uart1_config2 = {.phys = CALLIOPE_ADDR(0xA0180C)},
43 .uart1_divisorhi = 0xA01810, 46 .uart1_divisorhi = {.phys = CALLIOPE_ADDR(0xA01810)},
44 .uart1_divisorlo = 0xA01814, 47 .uart1_divisorlo = {.phys = CALLIOPE_ADDR(0xA01814)},
45 .uart1_data = 0xA01818, 48 .uart1_data = {.phys = CALLIOPE_ADDR(0xA01818)},
46 .uart1_status = 0xA0181C, 49 .uart1_status = {.phys = CALLIOPE_ADDR(0xA0181C)},
47 50
48 .int_stat_3 = 0xA02800, 51 .int_stat_3 = {.phys = CALLIOPE_ADDR(0xA02800)},
49 .int_stat_2 = 0xA02804, 52 .int_stat_2 = {.phys = CALLIOPE_ADDR(0xA02804)},
50 .int_stat_1 = 0xA02808, 53 .int_stat_1 = {.phys = CALLIOPE_ADDR(0xA02808)},
51 .int_stat_0 = 0xA0280c, 54 .int_stat_0 = {.phys = CALLIOPE_ADDR(0xA0280c)},
52 .int_config = 0xA02810, 55 .int_config = {.phys = CALLIOPE_ADDR(0xA02810)},
53 .int_int_scan = 0xA02818, 56 .int_int_scan = {.phys = CALLIOPE_ADDR(0xA02818)},
54 .ien_int_3 = 0xA02830, 57 .ien_int_3 = {.phys = CALLIOPE_ADDR(0xA02830)},
55 .ien_int_2 = 0xA02834, 58 .ien_int_2 = {.phys = CALLIOPE_ADDR(0xA02834)},
56 .ien_int_1 = 0xA02838, 59 .ien_int_1 = {.phys = CALLIOPE_ADDR(0xA02838)},
57 .ien_int_0 = 0xA0283c, 60 .ien_int_0 = {.phys = CALLIOPE_ADDR(0xA0283c)},
58 .int_level_3_3 = 0xA02880, 61 .int_level_3_3 = {.phys = CALLIOPE_ADDR(0xA02880)},
59 .int_level_3_2 = 0xA02884, 62 .int_level_3_2 = {.phys = CALLIOPE_ADDR(0xA02884)},
60 .int_level_3_1 = 0xA02888, 63 .int_level_3_1 = {.phys = CALLIOPE_ADDR(0xA02888)},
61 .int_level_3_0 = 0xA0288c, 64 .int_level_3_0 = {.phys = CALLIOPE_ADDR(0xA0288c)},
62 .int_level_2_3 = 0xA02890, 65 .int_level_2_3 = {.phys = CALLIOPE_ADDR(0xA02890)},
63 .int_level_2_2 = 0xA02894, 66 .int_level_2_2 = {.phys = CALLIOPE_ADDR(0xA02894)},
64 .int_level_2_1 = 0xA02898, 67 .int_level_2_1 = {.phys = CALLIOPE_ADDR(0xA02898)},
65 .int_level_2_0 = 0xA0289c, 68 .int_level_2_0 = {.phys = CALLIOPE_ADDR(0xA0289c)},
66 .int_level_1_3 = 0xA028a0, 69 .int_level_1_3 = {.phys = CALLIOPE_ADDR(0xA028a0)},
67 .int_level_1_2 = 0xA028a4, 70 .int_level_1_2 = {.phys = CALLIOPE_ADDR(0xA028a4)},
68 .int_level_1_1 = 0xA028a8, 71 .int_level_1_1 = {.phys = CALLIOPE_ADDR(0xA028a8)},
69 .int_level_1_0 = 0xA028ac, 72 .int_level_1_0 = {.phys = CALLIOPE_ADDR(0xA028ac)},
70 .int_level_0_3 = 0xA028b0, 73 .int_level_0_3 = {.phys = CALLIOPE_ADDR(0xA028b0)},
71 .int_level_0_2 = 0xA028b4, 74 .int_level_0_2 = {.phys = CALLIOPE_ADDR(0xA028b4)},
72 .int_level_0_1 = 0xA028b8, 75 .int_level_0_1 = {.phys = CALLIOPE_ADDR(0xA028b8)},
73 .int_level_0_0 = 0xA028bc, 76 .int_level_0_0 = {.phys = CALLIOPE_ADDR(0xA028bc)},
74 .int_docsis_en = 0xA028F4, 77 .int_docsis_en = {.phys = CALLIOPE_ADDR(0xA028F4)},
75 78
76 .mips_pll_setup = 0x980000, 79 .mips_pll_setup = {.phys = CALLIOPE_ADDR(0x980000)},
77 .usb_fs = 0x980030, /* -default 72800028- */ 80 .usb_fs = {.phys = CALLIOPE_ADDR(0x980030)},
78 .test_bus = 0x9800CC, 81 .test_bus = {.phys = CALLIOPE_ADDR(0x9800CC)},
79 .crt_spare = 0x9800d4, 82 .crt_spare = {.phys = CALLIOPE_ADDR(0x9800d4)},
80 .usb2_ohci_int_mask = 0x9A000c, 83 .usb2_ohci_int_mask = {.phys = CALLIOPE_ADDR(0x9A000c)},
81 .usb2_strap = 0x9A0014, 84 .usb2_strap = {.phys = CALLIOPE_ADDR(0x9A0014)},
82 .ehci_hcapbase = 0x9BFE00, 85 .ehci_hcapbase = {.phys = CALLIOPE_ADDR(0x9BFE00)},
83 .ohci_hc_revision = 0x9BFC00, 86 .ohci_hc_revision = {.phys = CALLIOPE_ADDR(0x9BFC00)},
84 .bcm1_bs_lmi_steer = 0x9E0004, 87 .bcm1_bs_lmi_steer = {.phys = CALLIOPE_ADDR(0x9E0004)},
85 .usb2_control = 0x9E0054, 88 .usb2_control = {.phys = CALLIOPE_ADDR(0x9E0054)},
86 .usb2_stbus_obc = 0x9BFF00, 89 .usb2_stbus_obc = {.phys = CALLIOPE_ADDR(0x9BFF00)},
87 .usb2_stbus_mess_size = 0x9BFF04, 90 .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
88 .usb2_stbus_chunk_size = 0x9BFF08, 91 .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
89 92
90 .pcie_regs = 0x000000, /* -doesn't exist- */ 93 .pcie_regs = {.phys = 0x000000}, /* -doesn't exist- */
91 .tim_ch = 0xA02C10, 94 .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
92 .tim_cl = 0xA02C14, 95 .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
93 .gpio_dout = 0xA02c20, 96 .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
94 .gpio_din = 0xA02c24, 97 .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
95 .gpio_dir = 0xA02c2C, 98 .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
96 .watchdog = 0xA02c30, 99 .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
97 .front_panel = 0x000000, /* -not used- */ 100 .front_panel = {.phys = 0x000000}, /* -not used- */
98}; 101};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 06:18:03 -0500