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authorJason Wessel <jason.wessel@windriver.com>2008-07-29 16:58:52 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-30 16:54:42 -0400
commit8d60a903d986ffa26c41f0092320a3b9da20bfaf (patch)
treef05a8ae48e275d55fcfd3acfb7b3b1b601da56ea /arch/mips/pmc-sierra
parent8f8da9adebdf04bfb3b812a7de8706fbf179fd2c (diff)
[MIPS] kgdb: Remove existing implementation
This patch explicitly removes the kgdb implementation, for mips which is intended to be followed by a patch that adds a kgdb implementation for MIPS that makes use of the kgdb core in the kernel. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pmc-sierra')
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c73
-rw-r--r--arch/mips/pmc-sierra/yosemite/Makefile1
-rw-r--r--arch/mips/pmc-sierra/yosemite/dbg_io.c180
-rw-r--r--arch/mips/pmc-sierra/yosemite/irq.c9
4 files changed, 0 insertions, 263 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index 9de34302e5f4..f7261628d8a6 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -38,68 +38,6 @@
38#include <msp_int.h> 38#include <msp_int.h>
39#include <msp_regs.h> 39#include <msp_regs.h>
40 40
41#ifdef CONFIG_KGDB
42/*
43 * kgdb uses serial port 1 so the console can remain on port 0.
44 * To use port 0 change the definition to read as follows:
45 * #define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART0_BASE)
46 */
47#define DEBUG_PORT_BASE KSEG1ADDR(MSP_UART1_BASE)
48
49int putDebugChar(char c)
50{
51 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
52 uint32_t val = (uint32_t)c;
53
54 local_irq_disable();
55 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
56 uart[0] = val;
57 while( !(uart[5] & 0x20) ); /* Wait for TXRDY */
58 local_irq_enable();
59
60 return 1;
61}
62
63char getDebugChar(void)
64{
65 volatile uint32_t *uart = (volatile uint32_t *)DEBUG_PORT_BASE;
66 uint32_t val;
67
68 while( !(uart[5] & 0x01) ); /* Wait for RXRDY */
69 val = uart[0];
70
71 return (char)val;
72}
73
74void initDebugPort(unsigned int uartclk, unsigned int baudrate)
75{
76 unsigned int baud_divisor = (uartclk + 8 * baudrate)/(16 * baudrate);
77
78 /* Enable FIFOs */
79 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
80 UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_4,
81 (char *)DEBUG_PORT_BASE + (UART_FCR * 4));
82
83 /* Select brtc divisor */
84 writeb(UART_LCR_DLAB, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
85
86 /* Store divisor lsb */
87 writeb(baud_divisor, (char *)DEBUG_PORT_BASE + (UART_TX * 4));
88
89 /* Store divisor msb */
90 writeb(baud_divisor >> 8, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
91
92 /* Set 8N1 mode */
93 writeb(UART_LCR_WLEN8, (char *)DEBUG_PORT_BASE + (UART_LCR * 4));
94
95 /* Disable flow control */
96 writeb(0, (char *)DEBUG_PORT_BASE + (UART_MCR * 4));
97
98 /* Disable receive interrupt(!) */
99 writeb(0, (char *)DEBUG_PORT_BASE + (UART_IER * 4));
100}
101#endif
102
103void __init msp_serial_setup(void) 41void __init msp_serial_setup(void)
104{ 42{
105 char *s; 43 char *s;
@@ -139,17 +77,6 @@ void __init msp_serial_setup(void)
139 case MACH_MSP7120_FPGA: 77 case MACH_MSP7120_FPGA:
140 /* Enable UART1 on MSP4200 and MSP7120 */ 78 /* Enable UART1 on MSP4200 and MSP7120 */
141 *GPIO_CFG2_REG = 0x00002299; 79 *GPIO_CFG2_REG = 0x00002299;
142
143#ifdef CONFIG_KGDB
144 /* Initialize UART1 for kgdb since PMON doesn't */
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk, 19200);
149 else
150 initDebugPort(uartclk, 57600);
151 }
152#endif
153 break; 80 break;
154 81
155 default: 82 default:
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
index 8fd9a04e3534..b16f95c3df65 100644
--- a/arch/mips/pmc-sierra/yosemite/Makefile
+++ b/arch/mips/pmc-sierra/yosemite/Makefile
@@ -4,7 +4,6 @@
4 4
5obj-y += irq.o prom.o py-console.o setup.o 5obj-y += irq.o prom.o py-console.o setup.o
6 6
7obj-$(CONFIG_KGDB) += dbg_io.o
8obj-$(CONFIG_SMP) += smp.o 7obj-$(CONFIG_SMP) += smp.o
9 8
10EXTRA_CFLAGS += -Werror 9EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/pmc-sierra/yosemite/dbg_io.c b/arch/mips/pmc-sierra/yosemite/dbg_io.c
deleted file mode 100644
index 6362c702e389..000000000000
--- a/arch/mips/pmc-sierra/yosemite/dbg_io.c
+++ /dev/null
@@ -1,180 +0,0 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * Support for KGDB for the Yosemite board. We make use of single serial
28 * port to be used for KGDB as well as console. The second serial port
29 * seems to be having a problem. Single IRQ is allocated for both the
30 * ports. Hence, the interrupt routing code needs to figure out whether
31 * the interrupt came from channel A or B.
32 */
33
34#include <asm/serial.h>
35
36/*
37 * Baud rate, Parity, Data and Stop bit settings for the
38 * serial port on the Yosemite. Note that the Early printk
39 * patch has been added. So, we should be all set to go
40 */
41#define YOSEMITE_BAUD_2400 2400
42#define YOSEMITE_BAUD_4800 4800
43#define YOSEMITE_BAUD_9600 9600
44#define YOSEMITE_BAUD_19200 19200
45#define YOSEMITE_BAUD_38400 38400
46#define YOSEMITE_BAUD_57600 57600
47#define YOSEMITE_BAUD_115200 115200
48
49#define YOSEMITE_PARITY_NONE 0
50#define YOSEMITE_PARITY_ODD 0x08
51#define YOSEMITE_PARITY_EVEN 0x18
52#define YOSEMITE_PARITY_MARK 0x28
53#define YOSEMITE_PARITY_SPACE 0x38
54
55#define YOSEMITE_DATA_5BIT 0x0
56#define YOSEMITE_DATA_6BIT 0x1
57#define YOSEMITE_DATA_7BIT 0x2
58#define YOSEMITE_DATA_8BIT 0x3
59
60#define YOSEMITE_STOP_1BIT 0x0
61#define YOSEMITE_STOP_2BIT 0x4
62
63/* This is crucial */
64#define SERIAL_REG_OFS 0x1
65
66#define SERIAL_RCV_BUFFER 0x0
67#define SERIAL_TRANS_HOLD 0x0
68#define SERIAL_SEND_BUFFER 0x0
69#define SERIAL_INTR_ENABLE (1 * SERIAL_REG_OFS)
70#define SERIAL_INTR_ID (2 * SERIAL_REG_OFS)
71#define SERIAL_DATA_FORMAT (3 * SERIAL_REG_OFS)
72#define SERIAL_LINE_CONTROL (3 * SERIAL_REG_OFS)
73#define SERIAL_MODEM_CONTROL (4 * SERIAL_REG_OFS)
74#define SERIAL_RS232_OUTPUT (4 * SERIAL_REG_OFS)
75#define SERIAL_LINE_STATUS (5 * SERIAL_REG_OFS)
76#define SERIAL_MODEM_STATUS (6 * SERIAL_REG_OFS)
77#define SERIAL_RS232_INPUT (6 * SERIAL_REG_OFS)
78#define SERIAL_SCRATCH_PAD (7 * SERIAL_REG_OFS)
79
80#define SERIAL_DIVISOR_LSB (0 * SERIAL_REG_OFS)
81#define SERIAL_DIVISOR_MSB (1 * SERIAL_REG_OFS)
82
83/*
84 * Functions to READ and WRITE to serial port 0
85 */
86#define SERIAL_READ(ofs) (*((volatile unsigned char*) \
87 (TITAN_SERIAL_BASE + ofs)))
88
89#define SERIAL_WRITE(ofs, val) ((*((volatile unsigned char*) \
90 (TITAN_SERIAL_BASE + ofs))) = val)
91
92/*
93 * Functions to READ and WRITE to serial port 1
94 */
95#define SERIAL_READ_1(ofs) (*((volatile unsigned char*) \
96 (TITAN_SERIAL_BASE_1 + ofs)))
97
98#define SERIAL_WRITE_1(ofs, val) ((*((volatile unsigned char*) \
99 (TITAN_SERIAL_BASE_1 + ofs))) = val)
100
101/*
102 * Second serial port initialization
103 */
104void init_second_port(void)
105{
106 /* Disable Interrupts */
107 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
108 SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0x0);
109
110 {
111 unsigned int divisor;
112
113 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x80);
114 divisor = TITAN_SERIAL_BASE_BAUD / YOSEMITE_BAUD_115200;
115 SERIAL_WRITE_1(SERIAL_DIVISOR_LSB, divisor & 0xff);
116
117 SERIAL_WRITE_1(SERIAL_DIVISOR_MSB,
118 (divisor & 0xff00) >> 8);
119 SERIAL_WRITE_1(SERIAL_LINE_CONTROL, 0x0);
120 }
121
122 SERIAL_WRITE_1(SERIAL_DATA_FORMAT, YOSEMITE_DATA_8BIT |
123 YOSEMITE_PARITY_NONE | YOSEMITE_STOP_1BIT);
124
125 /* Enable Interrupts */
126 SERIAL_WRITE_1(SERIAL_INTR_ENABLE, 0xf);
127}
128
129/* Initialize the serial port for KGDB debugging */
130void debugInit(unsigned int baud, unsigned char data, unsigned char parity,
131 unsigned char stop)
132{
133 /* Disable Interrupts */
134 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
135 SERIAL_WRITE(SERIAL_INTR_ENABLE, 0x0);
136
137 {
138 unsigned int divisor;
139
140 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x80);
141
142 divisor = TITAN_SERIAL_BASE_BAUD / baud;
143 SERIAL_WRITE(SERIAL_DIVISOR_LSB, divisor & 0xff);
144
145 SERIAL_WRITE(SERIAL_DIVISOR_MSB, (divisor & 0xff00) >> 8);
146 SERIAL_WRITE(SERIAL_LINE_CONTROL, 0x0);
147 }
148
149 SERIAL_WRITE(SERIAL_DATA_FORMAT, data | parity | stop);
150}
151
152static int remoteDebugInitialized = 0;
153
154unsigned char getDebugChar(void)
155{
156 if (!remoteDebugInitialized) {
157 remoteDebugInitialized = 1;
158 debugInit(YOSEMITE_BAUD_115200,
159 YOSEMITE_DATA_8BIT,
160 YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
161 }
162
163 while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x1) == 0);
164 return SERIAL_READ(SERIAL_RCV_BUFFER);
165}
166
167int putDebugChar(unsigned char byte)
168{
169 if (!remoteDebugInitialized) {
170 remoteDebugInitialized = 1;
171 debugInit(YOSEMITE_BAUD_115200,
172 YOSEMITE_DATA_8BIT,
173 YOSEMITE_PARITY_NONE, YOSEMITE_STOP_1BIT);
174 }
175
176 while ((SERIAL_READ(SERIAL_LINE_STATUS) & 0x20) == 0);
177 SERIAL_WRITE(SERIAL_SEND_BUFFER, byte);
178
179 return 1;
180}
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
index 4decc2807867..5f673eba142c 100644
--- a/arch/mips/pmc-sierra/yosemite/irq.c
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -141,10 +141,6 @@ asmlinkage void plat_irq_dispatch(void)
141 } 141 }
142} 142}
143 143
144#ifdef CONFIG_KGDB
145extern void init_second_port(void);
146#endif
147
148/* 144/*
149 * Initialize the next level interrupt handler 145 * Initialize the next level interrupt handler
150 */ 146 */
@@ -156,11 +152,6 @@ void __init arch_init_irq(void)
156 rm7k_cpu_irq_init(); 152 rm7k_cpu_irq_init();
157 rm9k_cpu_irq_init(); 153 rm9k_cpu_irq_init();
158 154
159#ifdef CONFIG_KGDB
160 /* At this point, initialize the second serial port */
161 init_second_port();
162#endif
163
164#ifdef CONFIG_GDB_CONSOLE 155#ifdef CONFIG_GDB_CONSOLE
165 register_gdb_console(); 156 register_gdb_console();
166#endif 157#endif
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