[PATCH] genirq: rename desc->handler to desc->chip

This patch-queue improves the generic IRQ layer to be truly generic, by adding
various abstractions and features to it, without impacting existing
functionality.

While the queue can be best described as "fix and improve everything in the
generic IRQ layer that we could think of", and thus it consists of many
smaller features and lots of cleanups, the one feature that stands out most is
the new 'irq chip' abstraction.

The irq-chip abstraction is about describing and coding and IRQ controller
driver by mapping its raw hardware capabilities [and quirks, if needed] in a
straightforward way, without having to think about "IRQ flow"
(level/edge/etc.) type of details.

This stands in contrast with the current 'irq-type' model of genirq
architectures, which 'mixes' raw hardware capabilities with 'flow' details.
The patchset supports both types of irq controller designs at once, and
converts i386 and x86_64 to the new irq-chip design.

As a bonus side-effect of the irq-chip approach, chained interrupt controllers
(master/slave PIC constructs, etc.) are now supported by design as well.

The end result of this patchset intends to be simpler architecture-level code
and more consolidation between architectures.

We reused many bits of code and many concepts from Russell King's ARM IRQ
layer, the merging of which was one of the motivations for this patchset.

This patch:

rename desc->handler to desc->chip.

Originally i did not want to do this, because it's a big patch.  But having
both "desc->handler", "desc->handle_irq" and "action->handler" caused a
large degree of confusion and made the code appear alot less clean than it
truly is.

I have also attempted a dual approach as well by introducing a
desc->chip alias - but that just wasnt robust enough and broke
frequently.

So lets get over with this quickly.  The conversion was done automatically
via scripts and converts all the code in the kernel.

This renaming patch is the first one amongst the patches, so that the
remaining patches can stay flexible and can be merged and split up
without having some big monolithic patch act as a merge barrier.

[akpm@osdl.org: build fix]
[akpm@osdl.org: another build fix]
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 5 insertions, 5 deletions

diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 39ee6314f627..8f18764a2359 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -236,7 +236,7 @@ void __init arch_init_irq(void)
         int configPR;
 
         for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
-                irq_desc[i].handler = &level_irq_type;
+                irq_desc[i].chip = &level_irq_type;
                 pnx8550_ack(i); /* mask the irq just in case  */
         }
 
@@ -273,7 +273,7 @@ void __init arch_init_irq(void)
                 /* mask/priority is still 0 so we will not get any
                  * interrupts until it is unmasked */
 
-                irq_desc[i].handler = &level_irq_type;
+                irq_desc[i].chip = &level_irq_type;
         }
 
         /* Priority level 0 */
@@ -282,12 +282,12 @@ void __init arch_init_irq(void)
         /* Set int vector table address */
         PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
 
-        irq_desc[MIPS_CPU_GIC_IRQ].handler = &level_irq_type;
+        irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type;
         setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
 
         /* init of Timer interrupts */
         for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) {
-                irq_desc[i].handler = &level_irq_type;
+                irq_desc[i].chip = &level_irq_type;
         }
 
         /* Stop Timer 1-3 */
@@ -295,7 +295,7 @@ void __init arch_init_irq(void)
         configPR |= 0x00000038;
         write_c0_config7(configPR);
 
-        irq_desc[MIPS_CPU_TIMER_IRQ].handler = &level_irq_type;
+        irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type;
         setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
 }