Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "MIPS updates:

   - All the things that didn't make 3.10.
   - Removes the Windriver PPMC platform.  Nobody will miss it.
   - Remove a workaround from kernel/irq/irqdomain.c which was there
     exclusivly for MIPS.  Patch by Grant Likely.
   - More small improvments for the SEAD 3 platform
   - Improvments on the BMIPS / SMP support for the BCM63xx series.
   - Various cleanups of dead leftovers.
   - Platform support for the Cavium Octeon-based EdgeRouter Lite.

  Two large KVM patchsets didn't make it for this pull request because
  their respective authors are vacationing"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (124 commits)
  MIPS: Kconfig: Add missing MODULES dependency to VPE_LOADER
  MIPS: BCM63xx: CLK: Add dummy clk_{set,round}_rate() functions
  MIPS: SEAD3: Disable L2 cache on SEAD-3.
  MIPS: BCM63xx: Enable second core SMP on BCM6328 if available
  MIPS: BCM63xx: Add SMP support to prom.c
  MIPS: define write{b,w,l,q}_relaxed
  MIPS: Expose missing pci_io{map,unmap} declarations
  MIPS: Malta: Update GCMP detection.
  Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"
  MIPS: APSP: Remove <asm/kspd.h>
  SSB: Kconfig: Amend SSB_EMBEDDED dependencies
  MIPS: microMIPS: Fix improper definition of ISA exception bit.
  MIPS: Don't try to decode microMIPS branch instructions where they cannot exist.
  MIPS: Declare emulate_load_store_microMIPS as a static function.
  MIPS: Fix typos and cleanup comment
  MIPS: Cleanup indentation and whitespace
  MIPS: BMIPS: support booting from physical CPU other than 0
  MIPS: Only set cpu_has_mmips if SYS_SUPPORTS_MICROMIPS
  MIPS: GIC: Fix gic_set_affinity infinite loop
  MIPS: Don't save/restore OCTEON wide multiplier state on syscalls.
  ...

5 files changed, 261 insertions, 42 deletions

diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 2cb1d315d225..c382042911dd 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_LASAT)		+= pci-lasat.o
 obj-$(CONFIG_MIPS_COBALT)       += fixup-cobalt.o
 obj-$(CONFIG_LEMOTE_FULOONG2E)  += fixup-fuloong2e.o ops-loongson2.o
 obj-$(CONFIG_LEMOTE_MACH2F)     += fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MIPS_MALTA)        += fixup-malta.o
+obj-$(CONFIG_MIPS_MALTA)        += fixup-malta.o pci-malta.o
 obj-$(CONFIG_PMC_MSP7120_GW)    += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_EVAL)  += fixup-pmcmsp.o ops-pmcmsp.o
 obj-$(CONFIG_PMC_MSP7120_FPGA)  += fixup-pmcmsp.o ops-pmcmsp.o
@@ -52,12 +52,11 @@ obj-$(CONFIG_TOSHIBA_RBTX4927)	+= fixup-rbtx4927.o
 obj-$(CONFIG_TOSHIBA_RBTX4938)  += fixup-rbtx4938.o
 obj-$(CONFIG_VICTOR_MPC30X)     += fixup-mpc30x.o
 obj-$(CONFIG_ZAO_CAPCELLA)      += fixup-capcella.o
-obj-$(CONFIG_WR_PPMC)           += fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)    += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
+obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o
 obj-$(CONFIG_CPU_XLR)           += pci-xlr.o
 obj-$(CONFIG_CPU_XLP)           += pci-xlp.o
 
 ifdef CONFIG_PCI_MSI
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
+obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o
 endif
diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
deleted file mode 100644
index 29737edd121f..000000000000
--- a/arch/mips/pci/fixup-wrppmc.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * fixup-wrppmc.c: PPMC board specific PCI fixup
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006, Wind River Inc. Rongkai.zhan (rongkai.zhan@windriver.com)
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/gt64120.h>
-
-/* PCI interrupt pins */
-#define PCI_INTA                1
-#define PCI_INTB                2
-#define PCI_INTC                3
-#define PCI_INTD                4
-
-#define PCI_SLOT_MAXNR  32 /* Each PCI bus has 32 physical slots */
-
-static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
-        /* 0    INTA   INTB   INTC   INTD */
-        [0] = {0, 0, 0, 0, 0},          /* Slot 0: GT64120 PCI bridge */
-        [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
-};
-
-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        return pci_irq_tab[slot][pin];
-}
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-        return 0;
-}
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 2eb954239bc5..151d9b5870bb 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(void)
         /* setup PCI to local bus access, used by PCI device to target
          * local RAM while bus mastering */
         bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
-        if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
+        if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
                 val = MPI_SP0_REMAP_ENABLE_MASK;
         else
                 val = 0;
@@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
         case BCM6328_CPU_ID:
         case BCM6362_CPU_ID:
                 return bcm63xx_register_pcie();
+        case BCM3368_CPU_ID:
         case BCM6348_CPU_ID:
         case BCM6358_CPU_ID:
         case BCM6368_CPU_ID:
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 6eb65e44d9e4..7b2ac81e1f59 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -217,6 +217,7 @@ static void pci_fixup_ioc3(struct pci_dev *d)
         pci_disable_swapping(d);
 }
 
+#ifdef CONFIG_NUMA
 int pcibus_to_node(struct pci_bus *bus)
 {
         struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
@@ -224,6 +225,7 @@ int pcibus_to_node(struct pci_bus *bus)
         return bc->nasid;
 }
 EXPORT_SYMBOL(pcibus_to_node);
+#endif /* CONFIG_NUMA */
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
         pci_fixup_ioc3);
diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c
new file mode 100644
index 000000000000..37134ddfeaa5
--- /dev/null
+++ b/arch/mips/pci/pci-malta.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
+ *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * MIPS boards specific PCI support.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/gt64120.h>
+#include <asm/gcmpregs.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/bonito64.h>
+#include <asm/mips-boards/msc01_pci.h>
+
+static struct resource bonito64_mem_resource = {
+        .name   = "Bonito PCI MEM",
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource bonito64_io_resource = {
+        .name   = "Bonito PCI I/O",
+        .start  = 0x00000000UL,
+        .end    = 0x000fffffUL,
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource gt64120_mem_resource = {
+        .name   = "GT-64120 PCI MEM",
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource gt64120_io_resource = {
+        .name   = "GT-64120 PCI I/O",
+        .flags  = IORESOURCE_IO,
+};
+
+static struct resource msc_mem_resource = {
+        .name   = "MSC PCI MEM",
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource msc_io_resource = {
+        .name   = "MSC PCI I/O",
+        .flags  = IORESOURCE_IO,
+};
+
+extern struct pci_ops bonito64_pci_ops;
+extern struct pci_ops gt64xxx_pci0_ops;
+extern struct pci_ops msc_pci_ops;
+
+static struct pci_controller bonito64_controller = {
+        .pci_ops        = &bonito64_pci_ops,
+        .io_resource    = &bonito64_io_resource,
+        .mem_resource   = &bonito64_mem_resource,
+        .io_offset      = 0x00000000UL,
+};
+
+static struct pci_controller gt64120_controller = {
+        .pci_ops        = &gt64xxx_pci0_ops,
+        .io_resource    = &gt64120_io_resource,
+        .mem_resource   = &gt64120_mem_resource,
+};
+
+static struct pci_controller msc_controller = {
+        .pci_ops        = &msc_pci_ops,
+        .io_resource    = &msc_io_resource,
+        .mem_resource   = &msc_mem_resource,
+};
+
+void __init mips_pcibios_init(void)
+{
+        struct pci_controller *controller;
+        resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;
+
+        switch (mips_revision_sconid) {
+        case MIPS_REVISION_SCON_GT64120:
+                /*
+                 * Due to a bug in the Galileo system controller, we need
+                 * to setup the PCI BAR for the Galileo internal registers.
+                 * This should be done in the bios/bootprom and will be
+                 * fixed in a later revision of YAMON (the MIPS boards
+                 * boot prom).
+                 */
+                GT_WRITE(GT_PCI0_CFGADDR_OFS,
+                         (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
+                         (0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
+                         (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
+                         ((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
+                         GT_PCI0_CFGADDR_CONFIGEN_BIT);
+
+                /* Perform the write */
+                GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
+
+                /* Set up resource ranges from the controller's registers.  */
+                start = GT_READ(GT_PCI0M0LD_OFS);
+                end = GT_READ(GT_PCI0M0HD_OFS);
+                map = GT_READ(GT_PCI0M0REMAP_OFS);
+                end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
+                start1 = GT_READ(GT_PCI0M1LD_OFS);
+                end1 = GT_READ(GT_PCI0M1HD_OFS);
+                map1 = GT_READ(GT_PCI0M1REMAP_OFS);
+                end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
+                /* Cannot support multiple windows, use the wider.  */
+                if (end1 - start1 > end - start) {
+                        start = start1;
+                        end = end1;
+                        map = map1;
+                }
+                mask = ~(start ^ end);
+                /* We don't support remapping with a discontiguous mask.  */
+                BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
+                       mask != ~((mask & -mask) - 1));
+                gt64120_mem_resource.start = start;
+                gt64120_mem_resource.end = end;
+                gt64120_controller.mem_offset = (start & mask) - (map & mask);
+                /* Addresses are 36-bit, so do shifts in the destinations.  */
+                gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
+                gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
+                gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
+                gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
+
+                start = GT_READ(GT_PCI0IOLD_OFS);
+                end = GT_READ(GT_PCI0IOHD_OFS);
+                map = GT_READ(GT_PCI0IOREMAP_OFS);
+                end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
+                mask = ~(start ^ end);
+                /* We don't support remapping with a discontiguous mask.  */
+                BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
+                       mask != ~((mask & -mask) - 1));
+                gt64120_io_resource.start = map & mask;
+                gt64120_io_resource.end = (map & mask) | ~mask;
+                gt64120_controller.io_offset = 0;
+                /* Addresses are 36-bit, so do shifts in the destinations.  */
+                gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
+                gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
+                gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
+
+                controller = &gt64120_controller;
+                break;
+
+        case MIPS_REVISION_SCON_BONITO:
+                /* Set up resource ranges from the controller's registers.  */
+                map = BONITO_PCIMAP;
+                map1 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) >>
+                       BONITO_PCIMAP_PCIMAP_LO0_SHIFT;
+                map2 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO1) >>
+                       BONITO_PCIMAP_PCIMAP_LO1_SHIFT;
+                map3 = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO2) >>
+                       BONITO_PCIMAP_PCIMAP_LO2_SHIFT;
+                /* Combine as many adjacent windows as possible.  */
+                map = map1;
+                start = BONITO_PCILO0_BASE;
+                end = 1;
+                if (map3 == map2 + 1) {
+                        map = map2;
+                        start = BONITO_PCILO1_BASE;
+                        end++;
+                }
+                if (map2 == map1 + 1) {
+                        map = map1;
+                        start = BONITO_PCILO0_BASE;
+                        end++;
+                }
+                bonito64_mem_resource.start = start;
+                bonito64_mem_resource.end = start +
+                                            BONITO_PCIMAP_WINBASE(end) - 1;
+                bonito64_controller.mem_offset = start -
+                                                 BONITO_PCIMAP_WINBASE(map);
+
+                controller = &bonito64_controller;
+                break;
+
+        case MIPS_REVISION_SCON_SOCIT:
+        case MIPS_REVISION_SCON_ROCIT:
+        case MIPS_REVISION_SCON_SOCITSC:
+        case MIPS_REVISION_SCON_SOCITSCP:
+                /* Set up resource ranges from the controller's registers.  */
+                MSC_READ(MSC01_PCI_SC2PMBASL, start);
+                MSC_READ(MSC01_PCI_SC2PMMSKL, mask);
+                MSC_READ(MSC01_PCI_SC2PMMAPL, map);
+                msc_mem_resource.start = start & mask;
+                msc_mem_resource.end = (start & mask) | ~mask;
+                msc_controller.mem_offset = (start & mask) - (map & mask);
+#ifdef CONFIG_MIPS_CMP
+                if (gcmp_niocu())
+                        gcmp_setregion(0, start, mask,
+                                GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+#endif
+                MSC_READ(MSC01_PCI_SC2PIOBASL, start);
+                MSC_READ(MSC01_PCI_SC2PIOMSKL, mask);
+                MSC_READ(MSC01_PCI_SC2PIOMAPL, map);
+                msc_io_resource.start = map & mask;
+                msc_io_resource.end = (map & mask) | ~mask;
+                msc_controller.io_offset = 0;
+                ioport_resource.end = ~mask;
+#ifdef CONFIG_MIPS_CMP
+                if (gcmp_niocu())
+                        gcmp_setregion(1, start, mask,
+                                GCMP_GCB_GCMPB_CMDEFTGT_IOCU1);
+#endif
+                /* If ranges overlap I/O takes precedence.  */
+                start = start & mask;
+                end = start | ~mask;
+                if ((start >= msc_mem_resource.start &&
+                     start <= msc_mem_resource.end) ||
+                    (end >= msc_mem_resource.start &&
+                     end <= msc_mem_resource.end)) {
+                        /* Use the larger space.  */
+                        start = max(start, msc_mem_resource.start);
+                        end = min(end, msc_mem_resource.end);
+                        if (start - msc_mem_resource.start >=
+                            msc_mem_resource.end - end)
+                                msc_mem_resource.end = start - 1;
+                        else
+                                msc_mem_resource.start = end + 1;
+                }
+
+                controller = &msc_controller;
+                break;
+        default:
+                return;
+        }
+
+        /* Change start address to avoid conflicts with ACPI and SMB devices */
+        if (controller->io_resource->start < 0x00002000UL)
+                controller->io_resource->start = 0x00002000UL;
+
+        iomem_resource.end &= 0xfffffffffULL;                   /* 64 GB */
+        ioport_resource.end = controller->io_resource->end;
+
+        controller->io_map_base = mips_io_port_base;
+
+        register_pci_controller(controller);
+}