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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:59:30 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:22 -0500
commit7034228792cc561e79ff8600f02884bd4c80e287 (patch)
tree89b77af37d087d9de236fc5d21f60bf552d0a2c6 /arch/mips/pci
parent405ab01c70e18058d9c01a1256769a61fc65413e (diff)
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile4
-rw-r--r--arch/mips/pci/fixup-cobalt.c28
-rw-r--r--arch/mips/pci/fixup-emma2rh.c2
-rw-r--r--arch/mips/pci/fixup-fuloong2e.c8
-rw-r--r--arch/mips/pci/fixup-ip32.c14
-rw-r--r--arch/mips/pci/fixup-lemote2f.c14
-rw-r--r--arch/mips/pci/fixup-malta.c14
-rw-r--r--arch/mips/pci/fixup-pmcmsp.c224
-rw-r--r--arch/mips/pci/fixup-sni.c68
-rw-r--r--arch/mips/pci/fixup-tb0219.c2
-rw-r--r--arch/mips/pci/fixup-tb0287.c2
-rw-r--r--arch/mips/pci/fixup-wrppmc.c2
-rw-r--r--arch/mips/pci/ops-bcm63xx.c16
-rw-r--r--arch/mips/pci/ops-bonito64.c4
-rw-r--r--arch/mips/pci/ops-gt64xxx_pci0.c24
-rw-r--r--arch/mips/pci/ops-lantiq.c2
-rw-r--r--arch/mips/pci/ops-loongson2.c2
-rw-r--r--arch/mips/pci/ops-msc.c22
-rw-r--r--arch/mips/pci/ops-nile4.c2
-rw-r--r--arch/mips/pci/ops-pmcmsp.c450
-rw-r--r--arch/mips/pci/ops-rc32434.c2
-rw-r--r--arch/mips/pci/ops-sni.c8
-rw-r--r--arch/mips/pci/ops-tx4927.c8
-rw-r--r--arch/mips/pci/ops-vr41xx.c6
-rw-r--r--arch/mips/pci/pci-alchemy.c6
-rw-r--r--arch/mips/pci/pci-ar724x.c20
-rw-r--r--arch/mips/pci/pci-bcm1480.c8
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c6
-rw-r--r--arch/mips/pci/pci-bcm47xx.c2
-rw-r--r--arch/mips/pci/pci-bcm63xx.c62
-rw-r--r--arch/mips/pci/pci-bcm63xx.h2
-rw-r--r--arch/mips/pci/pci-ip27.c8
-rw-r--r--arch/mips/pci/pci-ip32.c6
-rw-r--r--arch/mips/pci/pci-lasat.c26
-rw-r--r--arch/mips/pci/pci-octeon.c30
-rw-r--r--arch/mips/pci/pci-rc32434.c6
-rw-r--r--arch/mips/pci/pci-sb1250.c8
-rw-r--r--arch/mips/pci/pci-vr41xx.c22
-rw-r--r--arch/mips/pci/pci-vr41xx.h2
-rw-r--r--arch/mips/pci/pci-xlp.c32
-rw-r--r--arch/mips/pci/pci-xlr.c34
-rw-r--r--arch/mips/pci/pci.c4
-rw-r--r--arch/mips/pci/pcie-octeon.c58
43 files changed, 635 insertions, 635 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 998554f37a17..2cb1d315d225 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
54obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 54obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 55obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o 56obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
57obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o 57obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
58obj-$(CONFIG_CPU_XLR) += pci-xlr.o 58obj-$(CONFIG_CPU_XLR) += pci-xlr.o
59obj-$(CONFIG_CPU_XLP) += pci-xlp.o 59obj-$(CONFIG_CPU_XLP) += pci-xlp.o
60 60
61ifdef CONFIG_PCI_MSI 61ifdef CONFIG_PCI_MSI
62obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o 62obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
63endif 63endif
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dd..a138e8ee5cfc 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -94,14 +94,14 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
94 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x-- 94 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
95 * 95 *
96 * On all machines prior to Q2, we had the STOP line disconnected 96 * On all machines prior to Q2, we had the STOP line disconnected
97 * from Galileo to VIA on PCI. The new Galileo does not function 97 * from Galileo to VIA on PCI. The new Galileo does not function
98 * correctly unless we have it connected. 98 * correctly unless we have it connected.
99 * 99 *
100 * Therefore we must set the disconnect/retry cycle values to 100 * Therefore we must set the disconnect/retry cycle values to
101 * something sensible when using the new Galileo. 101 * something sensible when using the new Galileo.
102 */ 102 */
103 103
104 printk(KERN_INFO "Galileo: revision %u\n", dev->revision); 104 printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
105 105
106#if 0 106#if 0
107 if (dev->revision >= 0x10) { 107 if (dev->revision >= 0x10) {
@@ -149,30 +149,30 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
149 qube_raq_via_board_id_fixup); 149 qube_raq_via_board_id_fixup);
150 150
151static char irq_tab_qube1[] __initdata = { 151static char irq_tab_qube1[] __initdata = {
152 [COBALT_PCICONF_CPU] = 0, 152 [COBALT_PCICONF_CPU] = 0,
153 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ, 153 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
154 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, 154 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
155 [COBALT_PCICONF_VIA] = 0, 155 [COBALT_PCICONF_VIA] = 0,
156 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 156 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
157 [COBALT_PCICONF_ETH1] = 0 157 [COBALT_PCICONF_ETH1] = 0
158}; 158};
159 159
160static char irq_tab_cobalt[] __initdata = { 160static char irq_tab_cobalt[] __initdata = {
161 [COBALT_PCICONF_CPU] = 0, 161 [COBALT_PCICONF_CPU] = 0,
162 [COBALT_PCICONF_ETH0] = ETH0_IRQ, 162 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
163 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ, 163 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
164 [COBALT_PCICONF_VIA] = 0, 164 [COBALT_PCICONF_VIA] = 0,
165 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 165 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
166 [COBALT_PCICONF_ETH1] = ETH1_IRQ 166 [COBALT_PCICONF_ETH1] = ETH1_IRQ
167}; 167};
168 168
169static char irq_tab_raq2[] __initdata = { 169static char irq_tab_raq2[] __initdata = {
170 [COBALT_PCICONF_CPU] = 0, 170 [COBALT_PCICONF_CPU] = 0,
171 [COBALT_PCICONF_ETH0] = ETH0_IRQ, 171 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
172 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ, 172 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
173 [COBALT_PCICONF_VIA] = 0, 173 [COBALT_PCICONF_VIA] = 0,
174 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ, 174 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
175 [COBALT_PCICONF_ETH1] = ETH1_IRQ 175 [COBALT_PCICONF_ETH1] = ETH1_IRQ
176}; 176};
177 177
178int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 178int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
index beaec32b02e5..19caf775c206 100644
--- a/arch/mips/pci/fixup-emma2rh.c
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -42,7 +42,7 @@
42 * 42 *
43 */ 43 */
44 44
45#define MAX_SLOT_NUM 10 45#define MAX_SLOT_NUM 10
46static unsigned char irq_map[][5] __initdata = { 46static unsigned char irq_map[][5] __initdata = {
47 [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC, 47 [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
48 MARKEINS_PCI_IRQ_INTD, 0,}, 48 MARKEINS_PCI_IRQ_INTD, 0,},
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 63ab4a042cd6..50da773faede 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -6,9 +6,9 @@
6 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology 6 * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
7 * Author: Fuxin Zhang, zhangfx@lemote.com 7 * Author: Fuxin Zhang, zhangfx@lemote.com
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
@@ -152,7 +152,7 @@ static void loongson2e_686b_func1_fixup(struct pci_dev *pdev)
152 /* disable read prefetch/write post buffers */ 152 /* disable read prefetch/write post buffers */
153 pci_write_config_byte(pdev, 0x41, 0x02); 153 pci_write_config_byte(pdev, 0x41, 0x02);
154 154
155 /* use 3/4 as fifo thresh hold */ 155 /* use 3/4 as fifo thresh hold */
156 pci_write_config_byte(pdev, 0x43, 0x0a); 156 pci_write_config_byte(pdev, 0x43, 0x0a);
157 pci_write_config_byte(pdev, 0x44, 0x00); 157 pci_write_config_byte(pdev, 0x44, 0x00);
158 158
diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c
index 190fffd08d3e..133685e215ee 100644
--- a/arch/mips/pci/fixup-ip32.c
+++ b/arch/mips/pci/fixup-ip32.c
@@ -22,13 +22,13 @@
22#define INTC MACEPCI_SHARED1_IRQ 22#define INTC MACEPCI_SHARED1_IRQ
23#define INTD MACEPCI_SHARED2_IRQ 23#define INTD MACEPCI_SHARED2_IRQ
24static char irq_tab_mace[][5] __initdata = { 24static char irq_tab_mace[][5] __initdata = {
25 /* Dummy INT#A INT#B INT#C INT#D */ 25 /* Dummy INT#A INT#B INT#C INT#D */
26 {0, 0, 0, 0, 0}, /* This is placeholder row - never used */ 26 {0, 0, 0, 0, 0}, /* This is placeholder row - never used */
27 {0, SCSI0, SCSI0, SCSI0, SCSI0}, 27 {0, SCSI0, SCSI0, SCSI0, SCSI0},
28 {0, SCSI1, SCSI1, SCSI1, SCSI1}, 28 {0, SCSI1, SCSI1, SCSI1, SCSI1},
29 {0, INTA0, INTB, INTC, INTD}, 29 {0, INTA0, INTB, INTC, INTD},
30 {0, INTA1, INTC, INTD, INTB}, 30 {0, INTA1, INTC, INTD, INTB},
31 {0, INTA2, INTD, INTB, INTC}, 31 {0, INTA2, INTD, INTB, INTC},
32}; 32};
33 33
34 34
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 519daaebb5da..95ab9a1bd010 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -31,7 +31,7 @@
31 31
32/* all the pci device has the PCIA pin, check the datasheet. */ 32/* all the pci device has the PCIA pin, check the datasheet. */
33static char irq_tab[][5] __initdata = { 33static char irq_tab[][5] __initdata = {
34 /* INTA INTB INTC INTD */ 34 /* INTA INTB INTC INTD */
35 {0, 0, 0, 0, 0}, /* 11: Unused */ 35 {0, 0, 0, 0, 0}, /* 11: Unused */
36 {0, 0, 0, 0, 0}, /* 12: Unused */ 36 {0, 0, 0, 0, 0}, /* 12: Unused */
37 {0, 0, 0, 0, 0}, /* 13: Unused */ 37 {0, 0, 0, 0, 0}, /* 13: Unused */
@@ -69,15 +69,15 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
69 case 2: 69 case 2:
70 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 70 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
71 CS5536_IDE_INTR); 71 CS5536_IDE_INTR);
72 return CS5536_IDE_INTR; /* for IDE */ 72 return CS5536_IDE_INTR; /* for IDE */
73 case 3: 73 case 3:
74 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 74 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
75 CS5536_ACC_INTR); 75 CS5536_ACC_INTR);
76 return CS5536_ACC_INTR; /* for AUDIO */ 76 return CS5536_ACC_INTR; /* for AUDIO */
77 case 4: /* for OHCI */ 77 case 4: /* for OHCI */
78 case 5: /* for EHCI */ 78 case 5: /* for EHCI */
79 case 6: /* for UDC */ 79 case 6: /* for UDC */
80 case 7: /* for OTG */ 80 case 7: /* for OTG */
81 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 81 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
82 CS5536_USB_INTR); 82 CS5536_USB_INTR);
83 return CS5536_USB_INTR; 83 return CS5536_USB_INTR;
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 75d03f6be3bd..07ada7f8441e 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -12,7 +12,7 @@ static char pci_irq[5] = {
12}; 12};
13 13
14static char irq_tab[][5] __initdata = { 14static char irq_tab[][5] __initdata = {
15 /* INTA INTB INTC INTD */ 15 /* INTA INTB INTC INTD */
16 {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */ 16 {0, 0, 0, 0, 0 }, /* 0: GT64120 PCI bridge */
17 {0, 0, 0, 0, 0 }, /* 1: Unused */ 17 {0, 0, 0, 0, 0 }, /* 1: Unused */
18 {0, 0, 0, 0, 0 }, /* 2: Unused */ 18 {0, 0, 0, 0, 0 }, /* 2: Unused */
@@ -23,7 +23,7 @@ static char irq_tab[][5] __initdata = {
23 {0, 0, 0, 0, 0 }, /* 7: Unused */ 23 {0, 0, 0, 0, 0 }, /* 7: Unused */
24 {0, 0, 0, 0, 0 }, /* 8: Unused */ 24 {0, 0, 0, 0, 0 }, /* 8: Unused */
25 {0, 0, 0, 0, 0 }, /* 9: Unused */ 25 {0, 0, 0, 0, 0 }, /* 9: Unused */
26 {0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */ 26 {0, 0, 0, 0, PCID }, /* 10: PIIX4 USB */
27 {0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */ 27 {0, PCIB, 0, 0, 0 }, /* 11: AMD 79C973 Ethernet */
28 {0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */ 28 {0, PCIC, 0, 0, 0 }, /* 12: Crystal 4281 Sound */
29 {0, 0, 0, 0, 0 }, /* 13: Unused */ 29 {0, 0, 0, 0, 0 }, /* 13: Unused */
@@ -31,9 +31,9 @@ static char irq_tab[][5] __initdata = {
31 {0, 0, 0, 0, 0 }, /* 15: Unused */ 31 {0, 0, 0, 0, 0 }, /* 15: Unused */
32 {0, 0, 0, 0, 0 }, /* 16: Unused */ 32 {0, 0, 0, 0, 0 }, /* 16: Unused */
33 {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/ 33 {0, 0, 0, 0, 0 }, /* 17: Bonito/SOC-it PCI Bridge*/
34 {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */ 34 {0, PCIA, PCIB, PCIC, PCID }, /* 18: PCI Slot 1 */
35 {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */ 35 {0, PCIB, PCIC, PCID, PCIA }, /* 19: PCI Slot 2 */
36 {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */ 36 {0, PCIC, PCID, PCIA, PCIB }, /* 20: PCI Slot 3 */
37 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ 37 {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */
38}; 38};
39 39
@@ -54,8 +54,8 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
54{ 54{
55 unsigned char reg_val; 55 unsigned char reg_val;
56 static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */ 56 static int piixirqmap[16] = { /* PIIX PIRQC[A:D] irq mappings */
57 0, 0, 0, 3, 57 0, 0, 0, 3,
58 4, 5, 6, 7, 58 4, 5, 6, 7,
59 0, 9, 10, 11, 59 0, 9, 10, 11,
60 12, 0, 14, 15 60 12, 0, 14, 15
61 }; 61 };
diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c
index 65735b1b7665..fab405c21c2f 100644
--- a/arch/mips/pci/fixup-pmcmsp.c
+++ b/arch/mips/pci/fixup-pmcmsp.c
@@ -48,117 +48,117 @@
48#if defined(CONFIG_PMC_MSP7120_GW) 48#if defined(CONFIG_PMC_MSP7120_GW)
49/* Garibaldi Board IRQ wiring to PCI slots */ 49/* Garibaldi Board IRQ wiring to PCI slots */
50static char irq_tab[][5] __initdata = { 50static char irq_tab[][5] __initdata = {
51 /* INTA INTB INTC INTD */ 51 /* INTA INTB INTC INTD */
52 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */ 52 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
53 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */ 53 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
54 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */ 54 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
55 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */ 55 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
56 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */ 56 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
57 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */ 57 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
58 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */ 58 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
59 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */ 59 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
60 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */ 60 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
61 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */ 61 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
62 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */ 62 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
63 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */ 63 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
64 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */ 64 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
65 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */ 65 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
66 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */ 66 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
67 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */ 67 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
68 {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */ 68 {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
69 {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */ 69 {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
70 {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */ 70 {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
71 {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */ 71 {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
72 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */ 72 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
73 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */ 73 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
74 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */ 74 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
75 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */ 75 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
76 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */ 76 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
77 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */ 77 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
78 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */ 78 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
79 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */ 79 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
80 {0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */ 80 {0, IRQ4, IRQ4, 0, 0 }, /* 18 (AD[28]): slot 0 */
81 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */ 81 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
82 {0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */ 82 {0, IRQ5, IRQ5, 0, 0 }, /* 20 (AD[30]): slot 1 */
83 {0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */ 83 {0, IRQ6, IRQ6, 0, 0 } /* 21 (AD[31]): slot 2 */
84}; 84};
85 85
86#elif defined(CONFIG_PMC_MSP7120_EVAL) 86#elif defined(CONFIG_PMC_MSP7120_EVAL)
87 87
88/* MSP7120 Eval Board IRQ wiring to PCI slots */ 88/* MSP7120 Eval Board IRQ wiring to PCI slots */
89static char irq_tab[][5] __initdata = { 89static char irq_tab[][5] __initdata = {
90 /* INTA INTB INTC INTD */ 90 /* INTA INTB INTC INTD */
91 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */ 91 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
92 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */ 92 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
93 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */ 93 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
94 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */ 94 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
95 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */ 95 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
96 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */ 96 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
97 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */ 97 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
98 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */ 98 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
99 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */ 99 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
100 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */ 100 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
101 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */ 101 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
102 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */ 102 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
103 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */ 103 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
104 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */ 104 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
105 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */ 105 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
106 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */ 106 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
107 {0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */ 107 {0, IRQ6, IRQ6, 0, 0 }, /* 6 (AD[16]): slot 3 (mini) */
108 {0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */ 108 {0, IRQ5, IRQ5, 0, 0 }, /* 7 (AD[17]): slot 2 (mini) */
109 {0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */ 109 {0, IRQ4, IRQ4, IRQ4, IRQ4}, /* 8 (AD[18]): slot 0 (PCI) */
110 {0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */ 110 {0, IRQ5, IRQ5, IRQ5, IRQ5}, /* 9 (AD[19]): slot 1 (PCI) */
111 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */ 111 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
112 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */ 112 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
113 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */ 113 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
114 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */ 114 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
115 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */ 115 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
116 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */ 116 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
117 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */ 117 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
118 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */ 118 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
119 {0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */ 119 {0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
120 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */ 120 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
121 {0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */ 121 {0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
122 {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */ 122 {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
123}; 123};
124 124
125#else 125#else
126 126
127/* Unknown board -- don't assign any IRQs */ 127/* Unknown board -- don't assign any IRQs */
128static char irq_tab[][5] __initdata = { 128static char irq_tab[][5] __initdata = {
129 /* INTA INTB INTC INTD */ 129 /* INTA INTB INTC INTD */
130 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */ 130 {0, 0, 0, 0, 0 }, /* (AD[0]): Unused */
131 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */ 131 {0, 0, 0, 0, 0 }, /* (AD[1]): Unused */
132 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */ 132 {0, 0, 0, 0, 0 }, /* (AD[2]): Unused */
133 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */ 133 {0, 0, 0, 0, 0 }, /* (AD[3]): Unused */
134 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */ 134 {0, 0, 0, 0, 0 }, /* (AD[4]): Unused */
135 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */ 135 {0, 0, 0, 0, 0 }, /* (AD[5]): Unused */
136 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */ 136 {0, 0, 0, 0, 0 }, /* (AD[6]): Unused */
137 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */ 137 {0, 0, 0, 0, 0 }, /* (AD[7]): Unused */
138 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */ 138 {0, 0, 0, 0, 0 }, /* (AD[8]): Unused */
139 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */ 139 {0, 0, 0, 0, 0 }, /* (AD[9]): Unused */
140 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */ 140 {0, 0, 0, 0, 0 }, /* 0 (AD[10]): Unused */
141 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */ 141 {0, 0, 0, 0, 0 }, /* 1 (AD[11]): Unused */
142 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */ 142 {0, 0, 0, 0, 0 }, /* 2 (AD[12]): Unused */
143 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */ 143 {0, 0, 0, 0, 0 }, /* 3 (AD[13]): Unused */
144 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */ 144 {0, 0, 0, 0, 0 }, /* 4 (AD[14]): Unused */
145 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */ 145 {0, 0, 0, 0, 0 }, /* 5 (AD[15]): Unused */
146 {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */ 146 {0, 0, 0, 0, 0 }, /* 6 (AD[16]): Unused */
147 {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */ 147 {0, 0, 0, 0, 0 }, /* 7 (AD[17]): Unused */
148 {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */ 148 {0, 0, 0, 0, 0 }, /* 8 (AD[18]): Unused */
149 {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */ 149 {0, 0, 0, 0, 0 }, /* 9 (AD[19]): Unused */
150 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */ 150 {0, 0, 0, 0, 0 }, /* 10 (AD[20]): Unused */
151 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */ 151 {0, 0, 0, 0, 0 }, /* 11 (AD[21]): Unused */
152 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */ 152 {0, 0, 0, 0, 0 }, /* 12 (AD[22]): Unused */
153 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */ 153 {0, 0, 0, 0, 0 }, /* 13 (AD[23]): Unused */
154 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */ 154 {0, 0, 0, 0, 0 }, /* 14 (AD[24]): Unused */
155 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */ 155 {0, 0, 0, 0, 0 }, /* 15 (AD[25]): Unused */
156 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */ 156 {0, 0, 0, 0, 0 }, /* 16 (AD[26]): Unused */
157 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */ 157 {0, 0, 0, 0, 0 }, /* 17 (AD[27]): Unused */
158 {0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */ 158 {0, 0, 0, 0, 0 }, /* 18 (AD[28]): Unused */
159 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */ 159 {0, 0, 0, 0, 0 }, /* 19 (AD[29]): Unused */
160 {0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */ 160 {0, 0, 0, 0, 0 }, /* 20 (AD[30]): Unused */
161 {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */ 161 {0, 0, 0, 0, 0 } /* 21 (AD[31]): Unused */
162}; 162};
163#endif 163#endif
164 164
@@ -168,14 +168,14 @@ static char irq_tab[][5] __initdata = {
168 * _________________________________________________________________________ 168 * _________________________________________________________________________
169 * 169 *
170 * DESCRIPTION: Perform platform specific device initialization at 170 * DESCRIPTION: Perform platform specific device initialization at
171 * pci_enable_device() time. 171 * pci_enable_device() time.
172 * None are needed for the MSP7120 PCI Controller. 172 * None are needed for the MSP7120 PCI Controller.
173 * 173 *
174 * INPUTS: dev - structure describing the PCI device 174 * INPUTS: dev - structure describing the PCI device
175 * 175 *
176 * OUTPUTS: none 176 * OUTPUTS: none
177 * 177 *
178 * RETURNS: PCIBIOS_SUCCESSFUL 178 * RETURNS: PCIBIOS_SUCCESSFUL
179 * 179 *
180 ****************************************************************************/ 180 ****************************************************************************/
181int pcibios_plat_dev_init(struct pci_dev *dev) 181int pcibios_plat_dev_init(struct pci_dev *dev)
@@ -190,16 +190,16 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
190 * 190 *
191 * DESCRIPTION: Perform board supplied PCI IRQ mapping routine. 191 * DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
192 * 192 *
193 * INPUTS: dev - unused 193 * INPUTS: dev - unused
194 * slot - PCI slot. Identified by which bit of the AD[] bus 194 * slot - PCI slot. Identified by which bit of the AD[] bus
195 * drives the IDSEL line. AD[10] is 0, AD[31] is 195 * drives the IDSEL line. AD[10] is 0, AD[31] is
196 * slot 21. 196 * slot 21.
197 * pin - numbered using the scheme of the PCI_INTERRUPT_PIN 197 * pin - numbered using the scheme of the PCI_INTERRUPT_PIN
198 * field of the config header. 198 * field of the config header.
199 * 199 *
200 * OUTPUTS: none 200 * OUTPUTS: none
201 * 201 *
202 * RETURNS: IRQ number 202 * RETURNS: IRQ number
203 * 203 *
204 ****************************************************************************/ 204 ****************************************************************************/
205int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 205int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c
index 5c8a79bb2661..f67ebeeb4200 100644
--- a/arch/mips/pci/fixup-sni.c
+++ b/arch/mips/pci/fixup-sni.c
@@ -41,12 +41,12 @@
41 * Logic CL-GD5434 VGA is device 3. 41 * Logic CL-GD5434 VGA is device 3.
42 */ 42 */
43static char irq_tab_rm200[8][5] __initdata = { 43static char irq_tab_rm200[8][5] __initdata = {
44 /* INTA INTB INTC INTD */ 44 /* INTA INTB INTC INTD */
45 { 0, 0, 0, 0, 0 }, /* EISA bridge */ 45 { 0, 0, 0, 0, 0 }, /* EISA bridge */
46 { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */ 46 { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
47 { ETH, ETH, ETH, ETH, ETH }, /* Ethernet */ 47 { ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
48 { INTB, INTB, INTB, INTB, INTB }, /* VGA */ 48 { INTB, INTB, INTB, INTB, INTB }, /* VGA */
49 { 0, 0, 0, 0, 0 }, /* Unused */ 49 { 0, 0, 0, 0, 0 }, /* Unused */
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */ 50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */ 51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */ 52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
@@ -58,20 +58,20 @@ static char irq_tab_rm200[8][5] __initdata = {
58 * The VGA card is optional for RM300 systems. 58 * The VGA card is optional for RM300 systems.
59 */ 59 */
60static char irq_tab_rm300d[8][5] __initdata = { 60static char irq_tab_rm300d[8][5] __initdata = {
61 /* INTA INTB INTC INTD */ 61 /* INTA INTB INTC INTD */
62 { 0, 0, 0, 0, 0 }, /* EISA bridge */ 62 { 0, 0, 0, 0, 0 }, /* EISA bridge */
63 { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */ 63 { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */ 64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
65 { INTB, INTB, INTB, INTB, INTB }, /* VGA */ 65 { INTB, INTB, INTB, INTB, INTB }, /* VGA */
66 { 0, 0, 0, 0, 0 }, /* Unused */ 66 { 0, 0, 0, 0, 0 }, /* Unused */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */ 67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */ 68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */ 69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
70}; 70};
71 71
72static char irq_tab_rm300e[5][5] __initdata = { 72static char irq_tab_rm300e[5][5] __initdata = {
73 /* INTA INTB INTC INTD */ 73 /* INTA INTB INTC INTD */
74 { 0, 0, 0, 0, 0 }, /* HOST bridge */ 74 { 0, 0, 0, 0, 0 }, /* HOST bridge */
75 { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */ 75 { SCSI, SCSI, SCSI, SCSI, SCSI }, /* SCSI */
76 { 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */ 76 { 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */
77 { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */ 77 { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
@@ -97,30 +97,30 @@ static char irq_tab_rm300e[5][5] __initdata = {
97#define INTD PCIT_IRQ_INTD 97#define INTD PCIT_IRQ_INTD
98 98
99static char irq_tab_pcit[13][5] __initdata = { 99static char irq_tab_pcit[13][5] __initdata = {
100 /* INTA INTB INTC INTD */ 100 /* INTA INTB INTC INTD */
101 { 0, 0, 0, 0, 0 }, /* HOST bridge */ 101 { 0, 0, 0, 0, 0 }, /* HOST bridge */
102 { SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 }, /* SCSI */ 102 { SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 }, /* SCSI */
103 { SCSI1, SCSI1, SCSI1, SCSI1, SCSI1 }, /* SCSI */ 103 { SCSI1, SCSI1, SCSI1, SCSI1, SCSI1 }, /* SCSI */
104 { ETH, ETH, ETH, ETH, ETH }, /* Ethernet */ 104 { ETH, ETH, ETH, ETH, ETH }, /* Ethernet */
105 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */ 105 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
106 { 0, 0, 0, 0, 0 }, /* Unused */ 106 { 0, 0, 0, 0, 0 }, /* Unused */
107 { 0, 0, 0, 0, 0 }, /* Unused */ 107 { 0, 0, 0, 0, 0 }, /* Unused */
108 { 0, 0, 0, 0, 0 }, /* Unused */ 108 { 0, 0, 0, 0, 0 }, /* Unused */
109 { 0, INTA, INTB, INTC, INTD }, /* Slot 1 */ 109 { 0, INTA, INTB, INTC, INTD }, /* Slot 1 */
110 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */ 110 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
111 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */ 111 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
112 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */ 112 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
113 { 0, INTA, INTB, INTC, INTD }, /* Slot 5 */ 113 { 0, INTA, INTB, INTC, INTD }, /* Slot 5 */
114}; 114};
115 115
116static char irq_tab_pcit_cplus[13][5] __initdata = { 116static char irq_tab_pcit_cplus[13][5] __initdata = {
117 /* INTA INTB INTC INTD */ 117 /* INTA INTB INTC INTD */
118 { 0, 0, 0, 0, 0 }, /* HOST bridge */ 118 { 0, 0, 0, 0, 0 }, /* HOST bridge */
119 { 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */ 119 { 0, INTB, INTC, INTD, INTA }, /* PCI Slot 9 */
120 { 0, 0, 0, 0, 0 }, /* PCI-EISA */ 120 { 0, 0, 0, 0, 0 }, /* PCI-EISA */
121 { 0, 0, 0, 0, 0 }, /* Unused */ 121 { 0, 0, 0, 0, 0 }, /* Unused */
122 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */ 122 { 0, INTA, INTB, INTC, INTD }, /* PCI-PCI bridge */
123 { 0, INTB, INTC, INTD, INTA }, /* fixup */ 123 { 0, INTB, INTC, INTD, INTA }, /* fixup */
124}; 124};
125 125
126static inline int is_rm300_revd(void) 126static inline int is_rm300_revd(void)
@@ -146,18 +146,18 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
146 } 146 }
147 return irq_tab_pcit_cplus[slot][pin]; 147 return irq_tab_pcit_cplus[slot][pin];
148 case SNI_BRD_PCI_TOWER: 148 case SNI_BRD_PCI_TOWER:
149 return irq_tab_pcit[slot][pin]; 149 return irq_tab_pcit[slot][pin];
150 150
151 case SNI_BRD_PCI_MTOWER: 151 case SNI_BRD_PCI_MTOWER:
152 if (is_rm300_revd()) 152 if (is_rm300_revd())
153 return irq_tab_rm300d[slot][pin]; 153 return irq_tab_rm300d[slot][pin];
154 /* fall through */ 154 /* fall through */
155 155
156 case SNI_BRD_PCI_DESKTOP: 156 case SNI_BRD_PCI_DESKTOP:
157 return irq_tab_rm200[slot][pin]; 157 return irq_tab_rm200[slot][pin];
158 158
159 case SNI_BRD_PCI_MTOWER_CPLUS: 159 case SNI_BRD_PCI_MTOWER_CPLUS:
160 return irq_tab_rm300e[slot][pin]; 160 return irq_tab_rm300e[slot][pin];
161 } 161 }
162 162
163 return 0; 163 return 0;
diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c
index 8084b17d4406..d0b0083fbd27 100644
--- a/arch/mips/pci/fixup-tb0219.c
+++ b/arch/mips/pci/fixup-tb0219.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups. 2 * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
3 * 3 *
4 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp> 4 * Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>
5 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org> 5 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c
index 2fe29db43725..8c5039ed75d7 100644
--- a/arch/mips/pci/fixup-tb0287.c
+++ b/arch/mips/pci/fixup-tb0287.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups. 2 * fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
3 * 3 *
4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org> 4 * Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
index 3d277549d5df..29737edd121f 100644
--- a/arch/mips/pci/fixup-wrppmc.c
+++ b/arch/mips/pci/fixup-wrppmc.c
@@ -20,7 +20,7 @@
20#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */ 20#define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
21 21
22static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = { 22static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
23 /* 0 INTA INTB INTC INTD */ 23 /* 0 INTA INTB INTC INTD */
24 [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */ 24 [0] = {0, 0, 0, 0, 0}, /* Slot 0: GT64120 PCI bridge */
25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, 25 [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
26}; 26};
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 4a156629e958..6144bb337e44 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -174,8 +174,8 @@ static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
174} 174}
175 175
176struct pci_ops bcm63xx_pci_ops = { 176struct pci_ops bcm63xx_pci_ops = {
177 .read = bcm63xx_pci_read, 177 .read = bcm63xx_pci_read,
178 .write = bcm63xx_pci_write 178 .write = bcm63xx_pci_write
179}; 179};
180 180
181#ifdef CONFIG_CARDBUS 181#ifdef CONFIG_CARDBUS
@@ -370,8 +370,8 @@ static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
370 return fake_cb_bridge_read(where, size, val); 370 return fake_cb_bridge_read(where, size, val);
371 } 371 }
372 372
373 /* a configuration cycle for the device behind the cardbus 373 /* a configuration cycle for the device behind the cardbus
374 * bridge is actually done as a type 0 cycle on the primary 374 * bridge is actually done as a type 0 cycle on the primary
375 * bus. This means that only one device can be on the cardbus 375 * bus. This means that only one device can be on the cardbus
376 * bus */ 376 * bus */
377 if (fake_cb_bridge_regs.bus_assigned && 377 if (fake_cb_bridge_regs.bus_assigned &&
@@ -403,8 +403,8 @@ static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
403} 403}
404 404
405struct pci_ops bcm63xx_cb_ops = { 405struct pci_ops bcm63xx_cb_ops = {
406 .read = bcm63xx_cb_read, 406 .read = bcm63xx_cb_read,
407 .write = bcm63xx_cb_write, 407 .write = bcm63xx_cb_write,
408}; 408};
409 409
410/* 410/*
@@ -523,6 +523,6 @@ static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
523 523
524 524
525struct pci_ops bcm63xx_pcie_ops = { 525struct pci_ops bcm63xx_pcie_ops = {
526 .read = bcm63xx_pcie_read, 526 .read = bcm63xx_pcie_read,
527 .write = bcm63xx_pcie_write 527 .write = bcm63xx_pcie_write
528}; 528};
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 1b3e03f20c54..830352e3aeda 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -26,7 +26,7 @@
26 26
27#include <asm/mips-boards/bonito64.h> 27#include <asm/mips-boards/bonito64.h>
28 28
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) 32#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
@@ -137,7 +137,7 @@ static int bonito64_pcibios_write(struct pci_bus *bus, unsigned int devfn,
137 data = val; 137 data = val;
138 else { 138 else {
139 if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 139 if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
140 where, &data)) 140 where, &data))
141 return -1; 141 return -1;
142 142
143 if (size == 1) 143 if (size == 1)
diff --git a/arch/mips/pci/ops-gt64xxx_pci0.c b/arch/mips/pci/ops-gt64xxx_pci0.c
index 3d896c5f413f..effcbda9f528 100644
--- a/arch/mips/pci/ops-gt64xxx_pci0.c
+++ b/arch/mips/pci/ops-gt64xxx_pci0.c
@@ -23,21 +23,21 @@
23 23
24#include <asm/gt64120.h> 24#include <asm/gt64120.h>
25 25
26#define PCI_ACCESS_READ 0 26#define PCI_ACCESS_READ 0
27#define PCI_ACCESS_WRITE 1 27#define PCI_ACCESS_WRITE 1
28 28
29/* 29/*
30 * PCI configuration cycle AD bus definition 30 * PCI configuration cycle AD bus definition
31 */ 31 */
32/* Type 0 */ 32/* Type 0 */
33#define PCI_CFG_TYPE0_REG_SHF 0 33#define PCI_CFG_TYPE0_REG_SHF 0
34#define PCI_CFG_TYPE0_FUNC_SHF 8 34#define PCI_CFG_TYPE0_FUNC_SHF 8
35 35
36/* Type 1 */ 36/* Type 1 */
37#define PCI_CFG_TYPE1_REG_SHF 0 37#define PCI_CFG_TYPE1_REG_SHF 0
38#define PCI_CFG_TYPE1_FUNC_SHF 8 38#define PCI_CFG_TYPE1_FUNC_SHF 8
39#define PCI_CFG_TYPE1_DEV_SHF 11 39#define PCI_CFG_TYPE1_DEV_SHF 11
40#define PCI_CFG_TYPE1_BUS_SHF 16 40#define PCI_CFG_TYPE1_BUS_SHF 16
41 41
42static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type, 42static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
@@ -50,7 +50,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
50 50
51 /* Clear cause register bits */ 51 /* Clear cause register bits */
52 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 52 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
53 GT_INTRCAUSE_TARABORT0_BIT)); 53 GT_INTRCAUSE_TARABORT0_BIT));
54 54
55 /* Setup address */ 55 /* Setup address */
56 GT_WRITE(GT_PCI0_CFGADDR_OFS, 56 GT_WRITE(GT_PCI0_CFGADDR_OFS,
@@ -87,7 +87,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
87 87
88 /* Clear bits */ 88 /* Clear bits */
89 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | 89 GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
90 GT_INTRCAUSE_TARABORT0_BIT)); 90 GT_INTRCAUSE_TARABORT0_BIT));
91 91
92 return -1; 92 return -1;
93 } 93 }
@@ -106,7 +106,7 @@ static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
106 u32 data = 0; 106 u32 data = 0;
107 107
108 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 108 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
109 where, &data)) 109 where, &data))
110 return PCIBIOS_DEVICE_NOT_FOUND; 110 return PCIBIOS_DEVICE_NOT_FOUND;
111 111
112 if (size == 1) 112 if (size == 1)
@@ -128,7 +128,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
128 data = val; 128 data = val;
129 else { 129 else {
130 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, 130 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
131 devfn, where, &data)) 131 devfn, where, &data))
132 return PCIBIOS_DEVICE_NOT_FOUND; 132 return PCIBIOS_DEVICE_NOT_FOUND;
133 133
134 if (size == 1) 134 if (size == 1)
@@ -140,7 +140,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
140 } 140 }
141 141
142 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, 142 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
143 where, &data)) 143 where, &data))
144 return PCIBIOS_DEVICE_NOT_FOUND; 144 return PCIBIOS_DEVICE_NOT_FOUND;
145 145
146 return PCIBIOS_SUCCESSFUL; 146 return PCIBIOS_SUCCESSFUL;
diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
index 1f2afb55cc71..16e7c2526d77 100644
--- a/arch/mips/pci/ops-lantiq.c
+++ b/arch/mips/pci/ops-lantiq.c
@@ -23,7 +23,7 @@
23#define LTQ_PCI_CFG_DEVNUM_SHF 11 23#define LTQ_PCI_CFG_DEVNUM_SHF 11
24#define LTQ_PCI_CFG_FUNNUM_SHF 8 24#define LTQ_PCI_CFG_FUNNUM_SHF 8
25 25
26#define PCI_ACCESS_READ 0 26#define PCI_ACCESS_READ 0
27#define PCI_ACCESS_WRITE 1 27#define PCI_ACCESS_WRITE 1
28 28
29static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, 29static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index afd221122d22..98254afa0287 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -24,7 +24,7 @@
24#include <cs5536/cs5536.h> 24#include <cs5536/cs5536.h>
25#endif 25#endif
26 26
27#define PCI_ACCESS_READ 0 27#define PCI_ACCESS_READ 0
28#define PCI_ACCESS_WRITE 1 28#define PCI_ACCESS_WRITE 1
29 29
30#define CFG_SPACE_REG(offset) \ 30#define CFG_SPACE_REG(offset) \
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 5d9fbb0f4670..92a8543361bb 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. 2 * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
3 * All rights reserved. 3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com> 4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com> 5 * Maciej W. Rozycki <macro@mips.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 * 7 *
8 * This program is free software; you can distribute it and/or modify it 8 * This program is free software; you can distribute it and/or modify it
@@ -28,21 +28,21 @@
28 28
29#include <asm/mips-boards/msc01_pci.h> 29#include <asm/mips-boards/msc01_pci.h>
30 30
31#define PCI_ACCESS_READ 0 31#define PCI_ACCESS_READ 0
32#define PCI_ACCESS_WRITE 1 32#define PCI_ACCESS_WRITE 1
33 33
34/* 34/*
35 * PCI configuration cycle AD bus definition 35 * PCI configuration cycle AD bus definition
36 */ 36 */
37/* Type 0 */ 37/* Type 0 */
38#define PCI_CFG_TYPE0_REG_SHF 0 38#define PCI_CFG_TYPE0_REG_SHF 0
39#define PCI_CFG_TYPE0_FUNC_SHF 8 39#define PCI_CFG_TYPE0_FUNC_SHF 8
40 40
41/* Type 1 */ 41/* Type 1 */
42#define PCI_CFG_TYPE1_REG_SHF 0 42#define PCI_CFG_TYPE1_REG_SHF 0
43#define PCI_CFG_TYPE1_FUNC_SHF 8 43#define PCI_CFG_TYPE1_FUNC_SHF 8
44#define PCI_CFG_TYPE1_DEV_SHF 11 44#define PCI_CFG_TYPE1_DEV_SHF 11
45#define PCI_CFG_TYPE1_BUS_SHF 16 45#define PCI_CFG_TYPE1_BUS_SHF 16
46 46
47static int msc_pcibios_config_access(unsigned char access_type, 47static int msc_pcibios_config_access(unsigned char access_type,
48 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 48 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
@@ -97,7 +97,7 @@ static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
97 return PCIBIOS_BAD_REGISTER_NUMBER; 97 return PCIBIOS_BAD_REGISTER_NUMBER;
98 98
99 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 99 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
100 &data)) 100 &data))
101 return -1; 101 return -1;
102 102
103 if (size == 1) 103 if (size == 1)
@@ -124,7 +124,7 @@ static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
124 data = val; 124 data = val;
125 else { 125 else {
126 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 126 if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
127 where, &data)) 127 where, &data))
128 return -1; 128 return -1;
129 129
130 if (size == 1) 130 if (size == 1)
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index 99929cf88419..499e35c3eb35 100644
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -6,7 +6,7 @@
6#include <asm/lasat/lasat.h> 6#include <asm/lasat/lasat.h>
7#include <asm/nile4.h> 7#include <asm/nile4.h>
8 8
9#define PCI_ACCESS_READ 0 9#define PCI_ACCESS_READ 0
10#define PCI_ACCESS_WRITE 1 10#define PCI_ACCESS_WRITE 1
11 11
12#define LO(reg) (reg / 4) 12#define LO(reg) (reg / 4)
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 389bf669d56e..d0b6f8399b07 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -9,8 +9,8 @@
9 * Much of the code is derived from the original DDB5074 port by 9 * Much of the code is derived from the original DDB5074 port by
10 * Geert Uytterhoeven <geert@sonycom.com> 10 * Geert Uytterhoeven <geert@sonycom.com>
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify it 12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the 13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your 14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version. 15 * option) any later version.
16 * 16 *
@@ -57,18 +57,18 @@ static void pci_proc_init(void);
57 * _________________________________________________________________________ 57 * _________________________________________________________________________
58 * 58 *
59 * DESCRIPTION: Prints the count of how many times each PCI 59 * DESCRIPTION: Prints the count of how many times each PCI
60 * interrupt has asserted. Can be invoked by the 60 * interrupt has asserted. Can be invoked by the
61 * /proc filesystem. 61 * /proc filesystem.
62 * 62 *
63 * INPUTS: page - part of STDOUT calculation 63 * INPUTS: page - part of STDOUT calculation
64 * off - part of STDOUT calculation 64 * off - part of STDOUT calculation
65 * count - part of STDOUT calculation 65 * count - part of STDOUT calculation
66 * data - unused 66 * data - unused
67 * 67 *
68 * OUTPUTS: start - new start location 68 * OUTPUTS: start - new start location
69 * eof - end of file pointer 69 * eof - end of file pointer
70 * 70 *
71 * RETURNS: len - STDOUT length 71 * RETURNS: len - STDOUT length
72 * 72 *
73 ****************************************************************************/ 73 ****************************************************************************/
74static int read_msp_pci_counts(char *page, char **start, off_t off, 74static int read_msp_pci_counts(char *page, char **start, off_t off,
@@ -106,21 +106,21 @@ static int read_msp_pci_counts(char *page, char **start, off_t off,
106 * _________________________________________________________________________ 106 * _________________________________________________________________________
107 * 107 *
108 * DESCRIPTION: Generates a configuration write cycle for debug purposes. 108 * DESCRIPTION: Generates a configuration write cycle for debug purposes.
109 * The IDSEL line asserted and location and data written are 109 * The IDSEL line asserted and location and data written are
110 * immaterial. Just want to be able to prove that a 110 * immaterial. Just want to be able to prove that a
111 * configuration write can be correctly generated on the 111 * configuration write can be correctly generated on the
112 * PCI bus. Intent is that this function by invocable from 112 * PCI bus. Intent is that this function by invocable from
113 * the /proc filesystem. 113 * the /proc filesystem.
114 * 114 *
115 * INPUTS: page - part of STDOUT calculation 115 * INPUTS: page - part of STDOUT calculation
116 * off - part of STDOUT calculation 116 * off - part of STDOUT calculation
117 * count - part of STDOUT calculation 117 * count - part of STDOUT calculation
118 * data - unused 118 * data - unused
119 * 119 *
120 * OUTPUTS: start - new start location 120 * OUTPUTS: start - new start location
121 * eof - end of file pointer 121 * eof - end of file pointer
122 * 122 *
123 * RETURNS: len - STDOUT length 123 * RETURNS: len - STDOUT length
124 * 124 *
125 ****************************************************************************/ 125 ****************************************************************************/
126static int gen_pci_cfg_wr(char *page, char **start, off_t off, 126static int gen_pci_cfg_wr(char *page, char **start, off_t off,
@@ -190,11 +190,11 @@ static int gen_pci_cfg_wr(char *page, char **start, off_t off,
190 * 190 *
191 * DESCRIPTION: Create entries in the /proc filesystem for debug access. 191 * DESCRIPTION: Create entries in the /proc filesystem for debug access.
192 * 192 *
193 * INPUTS: none 193 * INPUTS: none
194 * 194 *
195 * OUTPUTS: none 195 * OUTPUTS: none
196 * 196 *
197 * RETURNS: none 197 * RETURNS: none
198 * 198 *
199 ****************************************************************************/ 199 ****************************************************************************/
200static void pci_proc_init(void) 200static void pci_proc_init(void)
@@ -214,44 +214,44 @@ static DEFINE_SPINLOCK(bpci_lock);
214 * _________________________________________________________________________ 214 * _________________________________________________________________________
215 * 215 *
216 * DESCRIPTION: Defines the address range that pciauto() will use to 216 * DESCRIPTION: Defines the address range that pciauto() will use to
217 * assign to the I/O BARs of PCI devices. 217 * assign to the I/O BARs of PCI devices.
218 * 218 *
219 * Use the start and end addresses of the MSP7120 PCI Host 219 * Use the start and end addresses of the MSP7120 PCI Host
220 * Controller I/O space, in the form that they appear on the 220 * Controller I/O space, in the form that they appear on the
221 * PCI bus AFTER MSP7120 has performed address translation. 221 * PCI bus AFTER MSP7120 has performed address translation.
222 * 222 *
223 * For I/O accesses, MSP7120 ignores OATRAN and maps I/O 223 * For I/O accesses, MSP7120 ignores OATRAN and maps I/O
224 * accesses into the bottom 0xFFF region of address space, 224 * accesses into the bottom 0xFFF region of address space,
225 * so that is the range to put into the pci_io_resource 225 * so that is the range to put into the pci_io_resource
226 * struct. 226 * struct.
227 * 227 *
228 * In MSP4200, the start address was 0x04 instead of the 228 * In MSP4200, the start address was 0x04 instead of the
229 * expected 0x00. Will just assume there was a good reason 229 * expected 0x00. Will just assume there was a good reason
230 * for this! 230 * for this!
231 * 231 *
232 * NOTES: Linux, by default, will assign I/O space to the lowest 232 * NOTES: Linux, by default, will assign I/O space to the lowest
233 * region of address space. Since MSP7120 and Linux, 233 * region of address space. Since MSP7120 and Linux,
234 * by default, have no offset in between how they map, the 234 * by default, have no offset in between how they map, the
235 * io_offset element of pci_controller struct should be set 235 * io_offset element of pci_controller struct should be set
236 * to zero. 236 * to zero.
237 * ELEMENTS: 237 * ELEMENTS:
238 * name - String used for a meaningful name. 238 * name - String used for a meaningful name.
239 * 239 *
240 * start - Start address of MSP7120's I/O space, as MSP7120 presents 240 * start - Start address of MSP7120's I/O space, as MSP7120 presents
241 * the address on the PCI bus. 241 * the address on the PCI bus.
242 * 242 *
243 * end - End address of MSP7120's I/O space, as MSP7120 presents 243 * end - End address of MSP7120's I/O space, as MSP7120 presents
244 * the address on the PCI bus. 244 * the address on the PCI bus.
245 * 245 *
246 * flags - Attributes indicating the type of resource. In this case, 246 * flags - Attributes indicating the type of resource. In this case,
247 * indicate I/O space. 247 * indicate I/O space.
248 * 248 *
249 ****************************************************************************/ 249 ****************************************************************************/
250static struct resource pci_io_resource = { 250static struct resource pci_io_resource = {
251 .name = "pci IO space", 251 .name = "pci IO space",
252 .start = 0x04, 252 .start = 0x04,
253 .end = 0x0FFF, 253 .end = 0x0FFF,
254 .flags = IORESOURCE_IO /* I/O space */ 254 .flags = IORESOURCE_IO /* I/O space */
255}; 255};
256 256
257/***************************************************************************** 257/*****************************************************************************
@@ -260,26 +260,26 @@ static struct resource pci_io_resource = {
260 * _________________________________________________________________________ 260 * _________________________________________________________________________
261 * 261 *
262 * DESCRIPTION: Defines the address range that pciauto() will use to 262 * DESCRIPTION: Defines the address range that pciauto() will use to
263 * assign to the memory BARs of PCI devices. 263 * assign to the memory BARs of PCI devices.
264 * 264 *
265 * The .start and .end values are dependent upon how address 265 * The .start and .end values are dependent upon how address
266 * translation is performed by the OATRAN regiser. 266 * translation is performed by the OATRAN regiser.
267 * 267 *
268 * The values to use for .start and .end are the values 268 * The values to use for .start and .end are the values
269 * in the form they appear on the PCI bus AFTER MSP7120 has 269 * in the form they appear on the PCI bus AFTER MSP7120 has
270 * performed OATRAN address translation. 270 * performed OATRAN address translation.
271 * 271 *
272 * ELEMENTS: 272 * ELEMENTS:
273 * name - String used for a meaningful name. 273 * name - String used for a meaningful name.
274 * 274 *
275 * start - Start address of MSP7120's memory space, as MSP7120 presents 275 * start - Start address of MSP7120's memory space, as MSP7120 presents
276 * the address on the PCI bus. 276 * the address on the PCI bus.
277 * 277 *
278 * end - End address of MSP7120's memory space, as MSP7120 presents 278 * end - End address of MSP7120's memory space, as MSP7120 presents
279 * the address on the PCI bus. 279 * the address on the PCI bus.
280 * 280 *
281 * flags - Attributes indicating the type of resource. In this case, 281 * flags - Attributes indicating the type of resource. In this case,
282 * indicate memory space. 282 * indicate memory space.
283 * 283 *
284 ****************************************************************************/ 284 ****************************************************************************/
285static struct resource pci_mem_resource = { 285static struct resource pci_mem_resource = {
@@ -295,17 +295,17 @@ static struct resource pci_mem_resource = {
295 * _________________________________________________________________________ 295 * _________________________________________________________________________
296 * 296 *
297 * DESCRIPTION: PCI status interrupt handler. Updates the count of how 297 * DESCRIPTION: PCI status interrupt handler. Updates the count of how
298 * many times each status bit has been set, then clears 298 * many times each status bit has been set, then clears
299 * the status bits. If the appropriate macros are defined, 299 * the status bits. If the appropriate macros are defined,
300 * these counts can be viewed via the /proc filesystem. 300 * these counts can be viewed via the /proc filesystem.
301 * 301 *
302 * INPUTS: irq - unused 302 * INPUTS: irq - unused
303 * dev_id - unused 303 * dev_id - unused
304 * pt_regs - unused 304 * pt_regs - unused
305 * 305 *
306 * OUTPUTS: none 306 * OUTPUTS: none
307 * 307 *
308 * RETURNS: PCIBIOS_SUCCESSFUL - success 308 * RETURNS: PCIBIOS_SUCCESSFUL - success
309 * 309 *
310 ****************************************************************************/ 310 ****************************************************************************/
311static irqreturn_t bpci_interrupt(int irq, void *dev_id) 311static irqreturn_t bpci_interrupt(int irq, void *dev_id)
@@ -335,41 +335,41 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id)
335 * _________________________________________________________________________ 335 * _________________________________________________________________________
336 * 336 *
337 * DESCRIPTION: Performs a PCI configuration access (rd or wr), then 337 * DESCRIPTION: Performs a PCI configuration access (rd or wr), then
338 * checks that the access succeeded by querying MSP7120's 338 * checks that the access succeeded by querying MSP7120's
339 * PCI status bits. 339 * PCI status bits.
340 * 340 *
341 * INPUTS: 341 * INPUTS:
342 * access_type - kind of PCI configuration cycle to perform 342 * access_type - kind of PCI configuration cycle to perform
343 * (read or write). Legal values are 343 * (read or write). Legal values are
344 * PCI_ACCESS_WRITE and PCI_ACCESS_READ. 344 * PCI_ACCESS_WRITE and PCI_ACCESS_READ.
345 * 345 *
346 * bus - pointer to the bus number of the device to 346 * bus - pointer to the bus number of the device to
347 * be targeted for the configuration cycle. 347 * be targeted for the configuration cycle.
348 * The only element of the pci_bus structure 348 * The only element of the pci_bus structure
349 * used is bus->number. This argument determines 349 * used is bus->number. This argument determines
350 * if the configuration access will be Type 0 or 350 * if the configuration access will be Type 0 or
351 * Type 1. Since MSP7120 assumes itself to be the 351 * Type 1. Since MSP7120 assumes itself to be the
352 * PCI Host, any non-zero bus->number generates 352 * PCI Host, any non-zero bus->number generates
353 * a Type 1 access. 353 * a Type 1 access.
354 * 354 *
355 * devfn - this is an 8-bit field. The lower three bits 355 * devfn - this is an 8-bit field. The lower three bits
356 * specify the function number of the device to 356 * specify the function number of the device to
357 * be targeted for the configuration cycle, with 357 * be targeted for the configuration cycle, with
358 * all three-bit combinations being legal. The 358 * all three-bit combinations being legal. The
359 * upper five bits specify the device number, 359 * upper five bits specify the device number,
360 * with legal values being 10 to 31. 360 * with legal values being 10 to 31.
361 * 361 *
362 * where - address within the Configuration Header 362 * where - address within the Configuration Header
363 * space to access. 363 * space to access.
364 * 364 *
365 * data - for write accesses, contains the data to 365 * data - for write accesses, contains the data to
366 * write. 366 * write.
367 * 367 *
368 * OUTPUTS: 368 * OUTPUTS:
369 * data - for read accesses, contains the value read. 369 * data - for read accesses, contains the value read.
370 * 370 *
371 * RETURNS: PCIBIOS_SUCCESSFUL - success 371 * RETURNS: PCIBIOS_SUCCESSFUL - success
372 * -1 - access failure 372 * -1 - access failure
373 * 373 *
374 ****************************************************************************/ 374 ****************************************************************************/
375int msp_pcibios_config_access(unsigned char access_type, 375int msp_pcibios_config_access(unsigned char access_type,
@@ -429,7 +429,7 @@ int msp_pcibios_config_access(unsigned char access_type,
429 * for this Block Copy, called Block Copy 0 Fault (BC0F) and 429 * for this Block Copy, called Block Copy 0 Fault (BC0F) and
430 * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this 430 * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
431 * dedicated Block Copy block, so these two interrupts are now 431 * dedicated Block Copy block, so these two interrupts are now
432 * marked reserved. In case the Block Copy is resurrected in a 432 * marked reserved. In case the Block Copy is resurrected in a
433 * future design, maintain the code that treats these two interrupts 433 * future design, maintain the code that treats these two interrupts
434 * specially. 434 * specially.
435 * 435 *
@@ -439,7 +439,7 @@ int msp_pcibios_config_access(unsigned char access_type,
439 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F); 439 preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
440 440
441 /* Setup address that is to appear on PCI bus */ 441 /* Setup address that is to appear on PCI bus */
442 preg->config_addr = BPCI_CFGADDR_ENABLE | 442 preg->config_addr = BPCI_CFGADDR_ENABLE |
443 (bus_num << BPCI_CFGADDR_BUSNUM_SHF) | 443 (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
444 (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) | 444 (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
445 (where & 0xFC); 445 (where & 0xFC);
@@ -494,21 +494,21 @@ int msp_pcibios_config_access(unsigned char access_type,
494 * _________________________________________________________________________ 494 * _________________________________________________________________________
495 * 495 *
496 * DESCRIPTION: Read a byte from PCI configuration address spac 496 * DESCRIPTION: Read a byte from PCI configuration address spac
497 * Since the hardware can't address 8 bit chunks 497 * Since the hardware can't address 8 bit chunks
498 * directly, read a 32-bit chunk, then mask off extraneous 498 * directly, read a 32-bit chunk, then mask off extraneous
499 * bits. 499 * bits.
500 * 500 *
501 * INPUTS bus - structure containing attributes for the PCI bus 501 * INPUTS bus - structure containing attributes for the PCI bus
502 * that the read is destined for. 502 * that the read is destined for.
503 * devfn - device/function combination that the read is 503 * devfn - device/function combination that the read is
504 * destined for. 504 * destined for.
505 * where - register within the Configuration Header space 505 * where - register within the Configuration Header space
506 * to access. 506 * to access.
507 * 507 *
508 * OUTPUTS val - read data 508 * OUTPUTS val - read data
509 * 509 *
510 * RETURNS: PCIBIOS_SUCCESSFUL - success 510 * RETURNS: PCIBIOS_SUCCESSFUL - success
511 * -1 - read access failure 511 * -1 - read access failure
512 * 512 *
513 ****************************************************************************/ 513 ****************************************************************************/
514static int 514static int
@@ -541,22 +541,22 @@ msp_pcibios_read_config_byte(struct pci_bus *bus,
541 * _________________________________________________________________________ 541 * _________________________________________________________________________
542 * 542 *
543 * DESCRIPTION: Read a word (16 bits) from PCI configuration address space. 543 * DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
544 * Since the hardware can't address 16 bit chunks 544 * Since the hardware can't address 16 bit chunks
545 * directly, read a 32-bit chunk, then mask off extraneous 545 * directly, read a 32-bit chunk, then mask off extraneous
546 * bits. 546 * bits.
547 * 547 *
548 * INPUTS bus - structure containing attributes for the PCI bus 548 * INPUTS bus - structure containing attributes for the PCI bus
549 * that the read is destined for. 549 * that the read is destined for.
550 * devfn - device/function combination that the read is 550 * devfn - device/function combination that the read is
551 * destined for. 551 * destined for.
552 * where - register within the Configuration Header space 552 * where - register within the Configuration Header space
553 * to access. 553 * to access.
554 * 554 *
555 * OUTPUTS val - read data 555 * OUTPUTS val - read data
556 * 556 *
557 * RETURNS: PCIBIOS_SUCCESSFUL - success 557 * RETURNS: PCIBIOS_SUCCESSFUL - success
558 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address 558 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
559 * -1 - read access failure 559 * -1 - read access failure
560 * 560 *
561 ****************************************************************************/ 561 ****************************************************************************/
562static int 562static int
@@ -600,20 +600,20 @@ msp_pcibios_read_config_word(struct pci_bus *bus,
600 * _________________________________________________________________________ 600 * _________________________________________________________________________
601 * 601 *
602 * DESCRIPTION: Read a double word (32 bits) from PCI configuration 602 * DESCRIPTION: Read a double word (32 bits) from PCI configuration
603 * address space. 603 * address space.
604 * 604 *
605 * INPUTS bus - structure containing attributes for the PCI bus 605 * INPUTS bus - structure containing attributes for the PCI bus
606 * that the read is destined for. 606 * that the read is destined for.
607 * devfn - device/function combination that the read is 607 * devfn - device/function combination that the read is
608 * destined for. 608 * destined for.
609 * where - register within the Configuration Header space 609 * where - register within the Configuration Header space
610 * to access. 610 * to access.
611 * 611 *
612 * OUTPUTS val - read data 612 * OUTPUTS val - read data
613 * 613 *
614 * RETURNS: PCIBIOS_SUCCESSFUL - success 614 * RETURNS: PCIBIOS_SUCCESSFUL - success
615 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address 615 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
616 * -1 - read access failure 616 * -1 - read access failure
617 * 617 *
618 ****************************************************************************/ 618 ****************************************************************************/
619static int 619static int
@@ -652,21 +652,21 @@ msp_pcibios_read_config_dword(struct pci_bus *bus,
652 * _________________________________________________________________________ 652 * _________________________________________________________________________
653 * 653 *
654 * DESCRIPTION: Write a byte to PCI configuration address space. 654 * DESCRIPTION: Write a byte to PCI configuration address space.
655 * Since the hardware can't address 8 bit chunks 655 * Since the hardware can't address 8 bit chunks
656 * directly, a read-modify-write is performed. 656 * directly, a read-modify-write is performed.
657 * 657 *
658 * INPUTS bus - structure containing attributes for the PCI bus 658 * INPUTS bus - structure containing attributes for the PCI bus
659 * that the write is destined for. 659 * that the write is destined for.
660 * devfn - device/function combination that the write is 660 * devfn - device/function combination that the write is
661 * destined for. 661 * destined for.
662 * where - register within the Configuration Header space 662 * where - register within the Configuration Header space
663 * to access. 663 * to access.
664 * val - value to write 664 * val - value to write
665 * 665 *
666 * OUTPUTS none 666 * OUTPUTS none
667 * 667 *
668 * RETURNS: PCIBIOS_SUCCESSFUL - success 668 * RETURNS: PCIBIOS_SUCCESSFUL - success
669 * -1 - write access failure 669 * -1 - write access failure
670 * 670 *
671 ****************************************************************************/ 671 ****************************************************************************/
672static int 672static int
@@ -700,22 +700,22 @@ msp_pcibios_write_config_byte(struct pci_bus *bus,
700 * _________________________________________________________________________ 700 * _________________________________________________________________________
701 * 701 *
702 * DESCRIPTION: Write a word (16-bits) to PCI configuration address space. 702 * DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
703 * Since the hardware can't address 16 bit chunks 703 * Since the hardware can't address 16 bit chunks
704 * directly, a read-modify-write is performed. 704 * directly, a read-modify-write is performed.
705 * 705 *
706 * INPUTS bus - structure containing attributes for the PCI bus 706 * INPUTS bus - structure containing attributes for the PCI bus
707 * that the write is destined for. 707 * that the write is destined for.
708 * devfn - device/function combination that the write is 708 * devfn - device/function combination that the write is
709 * destined for. 709 * destined for.
710 * where - register within the Configuration Header space 710 * where - register within the Configuration Header space
711 * to access. 711 * to access.
712 * val - value to write 712 * val - value to write
713 * 713 *
714 * OUTPUTS none 714 * OUTPUTS none
715 * 715 *
716 * RETURNS: PCIBIOS_SUCCESSFUL - success 716 * RETURNS: PCIBIOS_SUCCESSFUL - success
717 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address 717 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
718 * -1 - write access failure 718 * -1 - write access failure
719 * 719 *
720 ****************************************************************************/ 720 ****************************************************************************/
721static int 721static int
@@ -753,21 +753,21 @@ msp_pcibios_write_config_word(struct pci_bus *bus,
753 * _________________________________________________________________________ 753 * _________________________________________________________________________
754 * 754 *
755 * DESCRIPTION: Write a double word (32-bits) to PCI configuration address 755 * DESCRIPTION: Write a double word (32-bits) to PCI configuration address
756 * space. 756 * space.
757 * 757 *
758 * INPUTS bus - structure containing attributes for the PCI bus 758 * INPUTS bus - structure containing attributes for the PCI bus
759 * that the write is destined for. 759 * that the write is destined for.
760 * devfn - device/function combination that the write is 760 * devfn - device/function combination that the write is
761 * destined for. 761 * destined for.
762 * where - register within the Configuration Header space 762 * where - register within the Configuration Header space
763 * to access. 763 * to access.
764 * val - value to write 764 * val - value to write
765 * 765 *
766 * OUTPUTS none 766 * OUTPUTS none
767 * 767 *
768 * RETURNS: PCIBIOS_SUCCESSFUL - success 768 * RETURNS: PCIBIOS_SUCCESSFUL - success
769 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address 769 * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
770 * -1 - write access failure 770 * -1 - write access failure
771 * 771 *
772 ****************************************************************************/ 772 ****************************************************************************/
773static int 773static int
@@ -794,22 +794,22 @@ msp_pcibios_write_config_dword(struct pci_bus *bus,
794 * _________________________________________________________________________ 794 * _________________________________________________________________________
795 * 795 *
796 * DESCRIPTION: Interface the PCI configuration read request with 796 * DESCRIPTION: Interface the PCI configuration read request with
797 * the appropriate function, based on how many bytes 797 * the appropriate function, based on how many bytes
798 * the read request is. 798 * the read request is.
799 * 799 *
800 * INPUTS bus - structure containing attributes for the PCI bus 800 * INPUTS bus - structure containing attributes for the PCI bus
801 * that the write is destined for. 801 * that the write is destined for.
802 * devfn - device/function combination that the write is 802 * devfn - device/function combination that the write is
803 * destined for. 803 * destined for.
804 * where - register within the Configuration Header space 804 * where - register within the Configuration Header space
805 * to access. 805 * to access.
806 * size - in units of bytes, should be 1, 2, or 4. 806 * size - in units of bytes, should be 1, 2, or 4.
807 * 807 *
808 * OUTPUTS val - value read, with any extraneous bytes masked 808 * OUTPUTS val - value read, with any extraneous bytes masked
809 * to zero. 809 * to zero.
810 * 810 *
811 * RETURNS: PCIBIOS_SUCCESSFUL - success 811 * RETURNS: PCIBIOS_SUCCESSFUL - success
812 * -1 - failure 812 * -1 - failure
813 * 813 *
814 ****************************************************************************/ 814 ****************************************************************************/
815int 815int
@@ -845,22 +845,22 @@ msp_pcibios_read_config(struct pci_bus *bus,
845 * _________________________________________________________________________ 845 * _________________________________________________________________________
846 * 846 *
847 * DESCRIPTION: Interface the PCI configuration write request with 847 * DESCRIPTION: Interface the PCI configuration write request with
848 * the appropriate function, based on how many bytes 848 * the appropriate function, based on how many bytes
849 * the read request is. 849 * the read request is.
850 * 850 *
851 * INPUTS bus - structure containing attributes for the PCI bus 851 * INPUTS bus - structure containing attributes for the PCI bus
852 * that the write is destined for. 852 * that the write is destined for.
853 * devfn - device/function combination that the write is 853 * devfn - device/function combination that the write is
854 * destined for. 854 * destined for.
855 * where - register within the Configuration Header space 855 * where - register within the Configuration Header space
856 * to access. 856 * to access.
857 * size - in units of bytes, should be 1, 2, or 4. 857 * size - in units of bytes, should be 1, 2, or 4.
858 * val - value to write 858 * val - value to write
859 * 859 *
860 * OUTPUTS: none 860 * OUTPUTS: none
861 * 861 *
862 * RETURNS: PCIBIOS_SUCCESSFUL - success 862 * RETURNS: PCIBIOS_SUCCESSFUL - success
863 * -1 - failure 863 * -1 - failure
864 * 864 *
865 ****************************************************************************/ 865 ****************************************************************************/
866int 866int
@@ -897,11 +897,11 @@ msp_pcibios_write_config(struct pci_bus *bus,
897 * _________________________________________________________________________ 897 * _________________________________________________________________________
898 * 898 *
899 * DESCRIPTION: structure to abstract the hardware specific PCI 899 * DESCRIPTION: structure to abstract the hardware specific PCI
900 * configuration accesses. 900 * configuration accesses.
901 * 901 *
902 * ELEMENTS: 902 * ELEMENTS:
903 * read - function for Linux to generate PCI Configuration reads. 903 * read - function for Linux to generate PCI Configuration reads.
904 * write - function for Linux to generate PCI Configuration writes. 904 * write - function for Linux to generate PCI Configuration writes.
905 * 905 *
906 ****************************************************************************/ 906 ****************************************************************************/
907struct pci_ops msp_pci_ops = { 907struct pci_ops msp_pci_ops = {
@@ -917,27 +917,27 @@ struct pci_ops msp_pci_ops = {
917 * Describes the attributes of the MSP7120 PCI Host Controller 917 * Describes the attributes of the MSP7120 PCI Host Controller
918 * 918 *
919 * ELEMENTS: 919 * ELEMENTS:
920 * pci_ops - abstracts the hardware specific PCI configuration 920 * pci_ops - abstracts the hardware specific PCI configuration
921 * accesses. 921 * accesses.
922 * 922 *
923 * mem_resource - address range pciauto() uses to assign to PCI device 923 * mem_resource - address range pciauto() uses to assign to PCI device
924 * memory BARs. 924 * memory BARs.
925 * 925 *
926 * mem_offset - offset between how MSP7120 outbound PCI memory 926 * mem_offset - offset between how MSP7120 outbound PCI memory
927 * transaction addresses appear on the PCI bus and how Linux 927 * transaction addresses appear on the PCI bus and how Linux
928 * wants to configure memory BARs of the PCI devices. 928 * wants to configure memory BARs of the PCI devices.
929 * MSP7120 does nothing funky, so just set to zero. 929 * MSP7120 does nothing funky, so just set to zero.
930 * 930 *
931 * io_resource - address range pciauto() uses to assign to PCI device 931 * io_resource - address range pciauto() uses to assign to PCI device
932 * I/O BARs. 932 * I/O BARs.
933 * 933 *
934 * io_offset - offset between how MSP7120 outbound PCI I/O 934 * io_offset - offset between how MSP7120 outbound PCI I/O
935 * transaction addresses appear on the PCI bus and how 935 * transaction addresses appear on the PCI bus and how
936 * Linux defaults to configure I/O BARs of the PCI devices. 936 * Linux defaults to configure I/O BARs of the PCI devices.
937 * MSP7120 maps outbound I/O accesses into the bottom 937 * MSP7120 maps outbound I/O accesses into the bottom
938 * bottom 4K of PCI address space (and ignores OATRAN). 938 * bottom 4K of PCI address space (and ignores OATRAN).
939 * Since the Linux default is to configure I/O BARs to the 939 * Since the Linux default is to configure I/O BARs to the
940 * bottom 4K, no special offset is needed. Just set to zero. 940 * bottom 4K, no special offset is needed. Just set to zero.
941 * 941 *
942 ****************************************************************************/ 942 ****************************************************************************/
943static struct pci_controller msp_pci_controller = { 943static struct pci_controller msp_pci_controller = {
@@ -955,7 +955,7 @@ static struct pci_controller msp_pci_controller = {
955 * _________________________________________________________________________ 955 * _________________________________________________________________________
956 * 956 *
957 * DESCRIPTION: Initialize the PCI Host Controller and register it with 957 * DESCRIPTION: Initialize the PCI Host Controller and register it with
958 * Linux so Linux can seize control of the PCI bus. 958 * Linux so Linux can seize control of the PCI bus.
959 * 959 *
960 ****************************************************************************/ 960 ****************************************************************************/
961void __init msp_pci_init(void) 961void __init msp_pci_init(void)
@@ -979,7 +979,7 @@ void __init msp_pci_init(void)
979 *(unsigned long *)QFLUSH_REG_1 = 3; 979 *(unsigned long *)QFLUSH_REG_1 = 3;
980 980
981 /* Configure PCI Host Controller. */ 981 /* Configure PCI Host Controller. */
982 preg->if_status = ~0; /* Clear cause register bits */ 982 preg->if_status = ~0; /* Clear cause register bits */
983 preg->config_addr = 0; /* Clear config access */ 983 preg->config_addr = 0; /* Clear config access */
984 preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */ 984 preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
985 preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */ 985 preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
index d1f8fa210ca1..7c7182e2350a 100644
--- a/arch/mips/pci/ops-rc32434.c
+++ b/arch/mips/pci/ops-rc32434.c
@@ -35,7 +35,7 @@
35#include <asm/mach-rc32434/rc32434.h> 35#include <asm/mach-rc32434/rc32434.h>
36#include <asm/mach-rc32434/pci.h> 36#include <asm/mach-rc32434/pci.h>
37 37
38#define PCI_ACCESS_READ 0 38#define PCI_ACCESS_READ 0
39#define PCI_ACCESS_WRITE 1 39#define PCI_ACCESS_WRITE 1
40 40
41 41
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index 97ed25b92edf..35daa7fe6571 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -14,8 +14,8 @@
14 14
15/* 15/*
16 * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device 16 * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
17 * address are decoded. We therefore manually have to reject attempts at 17 * address are decoded. We therefore manually have to reject attempts at
18 * reading outside this range. Being on the paranoid side we only do this 18 * reading outside this range. Being on the paranoid side we only do this
19 * test for bus 0 and hope forwarding and decoding work properly for any 19 * test for bus 0 and hope forwarding and decoding work properly for any
20 * subordinated busses. 20 * subordinated busses.
21 * 21 *
@@ -31,8 +31,8 @@ static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
31 31
32 *(volatile u32 *)PCIMT_CONFIG_ADDRESS = 32 *(volatile u32 *)PCIMT_CONFIG_ADDRESS =
33 ((busno & 0xff) << 16) | 33 ((busno & 0xff) << 16) |
34 ((devfn & 0xff) << 8) | 34 ((devfn & 0xff) << 8) |
35 (reg & 0xfc); 35 (reg & 0xfc);
36 36
37 return PCIBIOS_SUCCESSFUL; 37 return PCIBIOS_SUCCESSFUL;
38} 38}
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 0d69d6f4ea44..3d5df514d024 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -2,16 +2,16 @@
2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc. 2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
3 * 3 *
4 * Based on linux/arch/mips/pci/ops-tx4938.c, 4 * Based on linux/arch/mips/pci/ops-tx4938.c,
5 * linux/arch/mips/pci/fixup-rbtx4938.c, 5 * linux/arch/mips/pci/fixup-rbtx4938.c,
6 * linux/arch/mips/txx9/rbtx4938/setup.c, 6 * linux/arch/mips/txx9/rbtx4938/setup.c,
7 * and RBTX49xx patch from CELF patch archive. 7 * and RBTX49xx patch from CELF patch archive.
8 * 8 *
9 * 2003-2005 (c) MontaVista Software, Inc. 9 * 2003-2005 (c) MontaVista Software, Inc.
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007 11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify it 13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the 14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your 15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version. 16 * option) any later version.
17 */ 17 */
diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c
index 28962a7c6606..551128c7d927 100644
--- a/arch/mips/pci/ops-vr41xx.c
+++ b/arch/mips/pci/ops-vr41xx.c
@@ -33,7 +33,7 @@
33#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18) 33#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
34 34
35static inline int set_pci_configuration_address(unsigned char number, 35static inline int set_pci_configuration_address(unsigned char number,
36 unsigned int devfn, int where) 36 unsigned int devfn, int where)
37{ 37{
38 if (number == 0) { 38 if (number == 0) {
39 /* 39 /*
@@ -59,7 +59,7 @@ static inline int set_pci_configuration_address(unsigned char number,
59} 59}
60 60
61static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, 61static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
62 int size, uint32_t *val) 62 int size, uint32_t *val)
63{ 63{
64 uint32_t data; 64 uint32_t data;
65 65
@@ -87,7 +87,7 @@ static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
87} 87}
88 88
89static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, 89static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
90 int size, uint32_t val) 90 int size, uint32_t val)
91{ 91{
92 uint32_t data; 92 uint32_t data;
93 int shift; 93 int shift;
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index c4ea6cc55f94..38a80c83fd67 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -29,7 +29,7 @@
29#define PCI_ACCESS_WRITE 1 29#define PCI_ACCESS_WRITE 1
30 30
31struct alchemy_pci_context { 31struct alchemy_pci_context {
32 struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ 32 struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
33 void __iomem *regs; /* ctrl base */ 33 void __iomem *regs; /* ctrl base */
34 /* tools for wired entry for config space access */ 34 /* tools for wired entry for config space access */
35 unsigned long last_elo0; 35 unsigned long last_elo0;
@@ -381,7 +381,7 @@ static int alchemy_pci_probe(struct platform_device *pdev)
381 381
382 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 382 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383 if (!r) { 383 if (!r) {
384 dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); 384 dev_err(&pdev->dev, "no pcictl ctrl regs resource\n");
385 ret = -ENODEV; 385 ret = -ENODEV;
386 goto out1; 386 goto out1;
387 } 387 }
@@ -482,7 +482,7 @@ out:
482 482
483static struct platform_driver alchemy_pcictl_driver = { 483static struct platform_driver alchemy_pcictl_driver = {
484 .probe = alchemy_pci_probe, 484 .probe = alchemy_pci_probe,
485 .driver = { 485 .driver = {
486 .name = "alchemy-pci", 486 .name = "alchemy-pci",
487 .owner = THIS_MODULE, 487 .owner = THIS_MODULE,
488 }, 488 },
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index c11c75be2d7e..279585d6eca0 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -177,22 +177,22 @@ static struct pci_ops ar724x_pci_ops = {
177}; 177};
178 178
179static struct resource ar724x_io_resource = { 179static struct resource ar724x_io_resource = {
180 .name = "PCI IO space", 180 .name = "PCI IO space",
181 .start = 0, 181 .start = 0,
182 .end = 0, 182 .end = 0,
183 .flags = IORESOURCE_IO, 183 .flags = IORESOURCE_IO,
184}; 184};
185 185
186static struct resource ar724x_mem_resource = { 186static struct resource ar724x_mem_resource = {
187 .name = "PCI memory space", 187 .name = "PCI memory space",
188 .start = AR724X_PCI_MEM_BASE, 188 .start = AR724X_PCI_MEM_BASE,
189 .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1, 189 .end = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
190 .flags = IORESOURCE_MEM, 190 .flags = IORESOURCE_MEM,
191}; 191};
192 192
193static struct pci_controller ar724x_pci_controller = { 193static struct pci_controller ar724x_pci_controller = {
194 .pci_ops = &ar724x_pci_ops, 194 .pci_ops = &ar724x_pci_ops,
195 .io_resource = &ar724x_io_resource, 195 .io_resource = &ar724x_io_resource,
196 .mem_resource = &ar724x_mem_resource, 196 .mem_resource = &ar724x_mem_resource,
197}; 197};
198 198
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 37b52dc3d27e..e2e69e1e9fe1 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -54,8 +54,8 @@
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
57#define PCI_BUS_ENABLED 1 57#define PCI_BUS_ENABLED 1
58#define PCI_DEVICE_MODE 2 58#define PCI_DEVICE_MODE 2
59 59
60static int bcm1480_bus_status; 60static int bcm1480_bus_status;
61 61
@@ -194,7 +194,7 @@ struct pci_controller bcm1480_controller = {
194 .pci_ops = &bcm1480_pci_ops, 194 .pci_ops = &bcm1480_pci_ops,
195 .mem_resource = &bcm1480_mem_resource, 195 .mem_resource = &bcm1480_mem_resource,
196 .io_resource = &bcm1480_io_resource, 196 .io_resource = &bcm1480_io_resource,
197 .io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 197 .io_offset = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
198}; 198};
199 199
200 200
@@ -227,7 +227,7 @@ static int __init bcm1480_pcibios_init(void)
227 PCI_COMMAND)); 227 PCI_COMMAND));
228 if (!(cmdreg & PCI_COMMAND_MASTER)) { 228 if (!(cmdreg & PCI_COMMAND_MASTER)) {
229 printk 229 printk
230 ("PCI: Skipping PCI probe. Bus is not initialized.\n"); 230 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
231 iounmap(cfg_space); 231 iounmap(cfg_space);
232 return 1; /* XXX */ 232 return 1; /* XXX */
233 } 233 }
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index 50cc6e9e8240..1263c5e7dbe1 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -53,8 +53,8 @@
53 53
54static void *ht_cfg_space; 54static void *ht_cfg_space;
55 55
56#define PCI_BUS_ENABLED 1 56#define PCI_BUS_ENABLED 1
57#define PCI_DEVICE_MODE 2 57#define PCI_DEVICE_MODE 2
58 58
59static int bcm1480ht_bus_status; 59static int bcm1480ht_bus_status;
60 60
@@ -191,7 +191,7 @@ struct pci_controller bcm1480ht_controller = {
191 .io_resource = &bcm1480ht_io_resource, 191 .io_resource = &bcm1480ht_io_resource,
192 .index = 1, 192 .index = 1,
193 .get_busno = bcm1480ht_pcibios_get_busno, 193 .get_busno = bcm1480ht_pcibios_get_busno,
194 .io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES, 194 .io_offset = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
195}; 195};
196 196
197static int __init bcm1480ht_pcibios_init(void) 197static int __init bcm1480ht_pcibios_init(void)
diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
index c682468010c5..76f16eaed0ad 100644
--- a/arch/mips/pci/pci-bcm47xx.c
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -91,7 +91,7 @@ static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
91int pcibios_plat_dev_init(struct pci_dev *dev) 91int pcibios_plat_dev_init(struct pci_dev *dev)
92{ 92{
93#ifdef CONFIG_BCM47XX_SSB 93#ifdef CONFIG_BCM47XX_SSB
94 if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB) 94 if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_SSB)
95 return bcm47xx_pcibios_plat_dev_init_ssb(dev); 95 return bcm47xx_pcibios_plat_dev_init_ssb(dev);
96 else 96 else
97#endif 97#endif
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index ca179b6ff39b..88e781c6b5ba 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -25,21 +25,21 @@
25int bcm63xx_pci_enabled; 25int bcm63xx_pci_enabled;
26 26
27static struct resource bcm_pci_mem_resource = { 27static struct resource bcm_pci_mem_resource = {
28 .name = "bcm63xx PCI memory space", 28 .name = "bcm63xx PCI memory space",
29 .start = BCM_PCI_MEM_BASE_PA, 29 .start = BCM_PCI_MEM_BASE_PA,
30 .end = BCM_PCI_MEM_END_PA, 30 .end = BCM_PCI_MEM_END_PA,
31 .flags = IORESOURCE_MEM 31 .flags = IORESOURCE_MEM
32}; 32};
33 33
34static struct resource bcm_pci_io_resource = { 34static struct resource bcm_pci_io_resource = {
35 .name = "bcm63xx PCI IO space", 35 .name = "bcm63xx PCI IO space",
36 .start = BCM_PCI_IO_BASE_PA, 36 .start = BCM_PCI_IO_BASE_PA,
37#ifdef CONFIG_CARDBUS 37#ifdef CONFIG_CARDBUS
38 .end = BCM_PCI_IO_HALF_PA, 38 .end = BCM_PCI_IO_HALF_PA,
39#else 39#else
40 .end = BCM_PCI_IO_END_PA, 40 .end = BCM_PCI_IO_END_PA,
41#endif 41#endif
42 .flags = IORESOURCE_IO 42 .flags = IORESOURCE_IO
43}; 43};
44 44
45struct pci_controller bcm63xx_controller = { 45struct pci_controller bcm63xx_controller = {
@@ -55,17 +55,17 @@ struct pci_controller bcm63xx_controller = {
55 */ 55 */
56#ifdef CONFIG_CARDBUS 56#ifdef CONFIG_CARDBUS
57static struct resource bcm_cb_mem_resource = { 57static struct resource bcm_cb_mem_resource = {
58 .name = "bcm63xx Cardbus memory space", 58 .name = "bcm63xx Cardbus memory space",
59 .start = BCM_CB_MEM_BASE_PA, 59 .start = BCM_CB_MEM_BASE_PA,
60 .end = BCM_CB_MEM_END_PA, 60 .end = BCM_CB_MEM_END_PA,
61 .flags = IORESOURCE_MEM 61 .flags = IORESOURCE_MEM
62}; 62};
63 63
64static struct resource bcm_cb_io_resource = { 64static struct resource bcm_cb_io_resource = {
65 .name = "bcm63xx Cardbus IO space", 65 .name = "bcm63xx Cardbus IO space",
66 .start = BCM_PCI_IO_HALF_PA + 1, 66 .start = BCM_PCI_IO_HALF_PA + 1,
67 .end = BCM_PCI_IO_END_PA, 67 .end = BCM_PCI_IO_END_PA,
68 .flags = IORESOURCE_IO 68 .flags = IORESOURCE_IO
69}; 69};
70 70
71struct pci_controller bcm63xx_cb_controller = { 71struct pci_controller bcm63xx_cb_controller = {
@@ -76,17 +76,17 @@ struct pci_controller bcm63xx_cb_controller = {
76#endif 76#endif
77 77
78static struct resource bcm_pcie_mem_resource = { 78static struct resource bcm_pcie_mem_resource = {
79 .name = "bcm63xx PCIe memory space", 79 .name = "bcm63xx PCIe memory space",
80 .start = BCM_PCIE_MEM_BASE_PA, 80 .start = BCM_PCIE_MEM_BASE_PA,
81 .end = BCM_PCIE_MEM_END_PA, 81 .end = BCM_PCIE_MEM_END_PA,
82 .flags = IORESOURCE_MEM, 82 .flags = IORESOURCE_MEM,
83}; 83};
84 84
85static struct resource bcm_pcie_io_resource = { 85static struct resource bcm_pcie_io_resource = {
86 .name = "bcm63xx PCIe IO space", 86 .name = "bcm63xx PCIe IO space",
87 .start = 0, 87 .start = 0,
88 .end = 0, 88 .end = 0,
89 .flags = 0, 89 .flags = 0,
90}; 90};
91 91
92struct pci_controller bcm63xx_pcie_controller = { 92struct pci_controller bcm63xx_pcie_controller = {
@@ -111,7 +111,7 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
111 u32 tmp; 111 u32 tmp;
112 112
113 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; 113 tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
114 tmp |= MPI_PCICFGCTL_WRITEEN_MASK; 114 tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
115 bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); 115 bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG); 116 bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
117} 117}
@@ -211,7 +211,7 @@ static int __init bcm63xx_register_pci(void)
211 * first bytes to access it from CPU. 211 * first bytes to access it from CPU.
212 * 212 *
213 * this means that no io access from CPU should happen while 213 * this means that no io access from CPU should happen while
214 * we do a configuration cycle, but there's no way we can add 214 * we do a configuration cycle, but there's no way we can add
215 * a spinlock for each io access, so this is currently kind of 215 * a spinlock for each io access, so this is currently kind of
216 * broken on SMP. 216 * broken on SMP.
217 */ 217 */
@@ -244,9 +244,9 @@ static int __init bcm63xx_register_pci(void)
244 bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG); 244 bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
245#endif 245#endif
246 246
247 /* setup local bus to PCI access (IO memory), we have only 1 247 /* setup local bus to PCI access (IO memory), we have only 1
248 * IO window for both PCI and cardbus, but it cannot handle 248 * IO window for both PCI and cardbus, but it cannot handle
249 * both at the same time, assume standard PCI for now, if 249 * both at the same time, assume standard PCI for now, if
250 * cardbus card has IO zone, PCI fixup will change window to 250 * cardbus card has IO zone, PCI fixup will change window to
251 * cardbus */ 251 * cardbus */
252 val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; 252 val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
@@ -284,7 +284,7 @@ static int __init bcm63xx_register_pci(void)
284 bcm_mpi_writel(0, MPI_SP1_RANGE_REG); 284 bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
285 } 285 }
286 286
287 /* change host bridge retry counter to infinite number of 287 /* change host bridge retry counter to infinite number of
288 * retry, needed for some broadcom wifi cards with Silicon 288 * retry, needed for some broadcom wifi cards with Silicon
289 * Backplane bus where access to srom seems very slow */ 289 * Backplane bus where access to srom seems very slow */
290 val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); 290 val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
index e6736d558ac7..ffab4da7bd00 100644
--- a/arch/mips/pci/pci-bcm63xx.h
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -7,7 +7,7 @@
7#include <bcm63xx_dev_pci.h> 7#include <bcm63xx_dev_pci.h>
8 8
9/* 9/*
10 * Cardbus shares the PCI bus, but has no IDSEL, so a special id is 10 * Cardbus shares the PCI bus, but has no IDSEL, so a special id is
11 * reserved for it. If you have a standard PCI device at this id, you 11 * reserved for it. If you have a standard PCI device at this id, you
12 * need to change the following definition. 12 * need to change the following definition.
13 */ 13 */
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 7f4f49b09b5b..6eb65e44d9e4 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -30,7 +30,7 @@
30 30
31/* 31/*
32 * XXX: No kmalloc available when we do our crosstalk scan, 32 * XXX: No kmalloc available when we do our crosstalk scan,
33 * we should try to move it later in the boot process. 33 * we should try to move it later in the boot process.
34 */ 34 */
35static struct bridge_controller bridges[MAX_PCI_BUSSES]; 35static struct bridge_controller bridges[MAX_PCI_BUSSES];
36 36
@@ -103,7 +103,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
103 * swap pio's to pci mem and io space (big windows) 103 * swap pio's to pci mem and io space (big windows)
104 */ 104 */
105 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 105 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
106 BRIDGE_CTRL_MEM_SWAP; 106 BRIDGE_CTRL_MEM_SWAP;
107#ifdef CONFIG_PAGE_SIZE_4KB 107#ifdef CONFIG_PAGE_SIZE_4KB
108 bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE; 108 bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
109#else /* 16kB or larger */ 109#else /* 16kB or larger */
@@ -123,7 +123,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
123 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR; 123 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
124 bc->pci_int[slot] = -1; 124 bc->pci_int[slot] = -1;
125 } 125 }
126 bridge->b_wid_tflush; /* wait until Bridge PIO complete */ 126 bridge->b_wid_tflush; /* wait until Bridge PIO complete */
127 127
128 bc->base = bridge; 128 bc->base = bridge;
129 129
@@ -184,7 +184,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
184} 184}
185 185
186/* 186/*
187 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses 187 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
188 * to find the slot number in sense of the bridge device register. 188 * to find the slot number in sense of the bridge device register.
189 * XXX This also means multiple devices might rely on conflicting bridge 189 * XXX This also means multiple devices might rely on conflicting bridge
190 * settings. 190 * settings.
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 532b561b4442..b1e061f7fdc7 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -18,9 +18,9 @@
18 18
19/* 19/*
20 * Handle errors from the bridge. This includes master and target aborts, 20 * Handle errors from the bridge. This includes master and target aborts,
21 * various command and address errors, and the interrupt test. This gets 21 * various command and address errors, and the interrupt test. This gets
22 * registered on the bridge error irq. It's conceivable that some of these 22 * registered on the bridge error irq. It's conceivable that some of these
23 * conditions warrant a panic. Anybody care to say which ones? 23 * conditions warrant a panic. Anybody care to say which ones?
24 */ 24 */
25static irqreturn_t macepci_error(int irq, void *dev) 25static irqreturn_t macepci_error(int irq, void *dev)
26{ 26{
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index a98e543a514a..40d2797d2bc4 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -51,15 +51,15 @@ static int __init lasat_pci_setup(void)
51 51
52arch_initcall(lasat_pci_setup); 52arch_initcall(lasat_pci_setup);
53 53
54#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0) 54#define LASAT_IRQ_ETH1 (LASAT_IRQ_BASE + 0)
55#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1) 55#define LASAT_IRQ_ETH0 (LASAT_IRQ_BASE + 1)
56#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2) 56#define LASAT_IRQ_HDC (LASAT_IRQ_BASE + 2)
57#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3) 57#define LASAT_IRQ_COMP (LASAT_IRQ_BASE + 3)
58#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4) 58#define LASAT_IRQ_HDLC (LASAT_IRQ_BASE + 4)
59#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5) 59#define LASAT_IRQ_PCIA (LASAT_IRQ_BASE + 5)
60#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6) 60#define LASAT_IRQ_PCIB (LASAT_IRQ_BASE + 6)
61#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7) 61#define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7)
62#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8) 62#define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8)
63 63
64int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 64int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
65{ 65{
@@ -69,13 +69,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
69 case 3: 69 case 3:
70 return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4); 70 return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
71 case 4: 71 case 4:
72 return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */ 72 return LASAT_IRQ_ETH1; /* Ethernet 1 (LAN 2) */
73 case 5: 73 case 5:
74 return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */ 74 return LASAT_IRQ_ETH0; /* Ethernet 0 (LAN 1) */
75 case 6: 75 case 6:
76 return LASAT_IRQ_HDC; /* IDE controller */ 76 return LASAT_IRQ_HDC; /* IDE controller */
77 default: 77 default:
78 return 0xff; /* Illegal */ 78 return 0xff; /* Illegal */
79 } 79 }
80 80
81 return -1; 81 return -1;
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 5b5ed76c6f47..95c2ea815cac 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -30,8 +30,8 @@
30 * addresses. Use PCI endian swapping 1 so no address swapping is 30 * addresses. Use PCI endian swapping 1 so no address swapping is
31 * necessary. The Linux io routines will endian swap the data. 31 * necessary. The Linux io routines will endian swap the data.
32 */ 32 */
33#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull 33#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
34#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) 34#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
35 35
36/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ 36/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
37#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) 37#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
@@ -68,10 +68,10 @@ enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
68 * 68 *
69 * @dev: The Linux PCI device structure for the device to map 69 * @dev: The Linux PCI device structure for the device to map
70 * @slot: The slot number for this device on __BUS 0__. Linux 70 * @slot: The slot number for this device on __BUS 0__. Linux
71 * enumerates through all the bridges and figures out the 71 * enumerates through all the bridges and figures out the
72 * slot on Bus 0 where this device eventually hooks to. 72 * slot on Bus 0 where this device eventually hooks to.
73 * @pin: The PCI interrupt pin read from the device, then swizzled 73 * @pin: The PCI interrupt pin read from the device, then swizzled
74 * as it goes through each bridge. 74 * as it goes through each bridge.
75 * Returns Interrupt number for the device 75 * Returns Interrupt number for the device
76 */ 76 */
77int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 77int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
@@ -120,8 +120,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
120 /* Enable the PCIe normal error reporting */ 120 /* Enable the PCIe normal error reporting */
121 config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ 121 config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
122 config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ 122 config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
123 config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ 123 config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */
124 config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ 124 config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */
125 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); 125 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
126 126
127 /* Find the Advanced Error Reporting capability */ 127 /* Find the Advanced Error Reporting capability */
@@ -226,10 +226,10 @@ const char *octeon_get_pci_interrupts(void)
226 * 226 *
227 * @dev: The Linux PCI device structure for the device to map 227 * @dev: The Linux PCI device structure for the device to map
228 * @slot: The slot number for this device on __BUS 0__. Linux 228 * @slot: The slot number for this device on __BUS 0__. Linux
229 * enumerates through all the bridges and figures out the 229 * enumerates through all the bridges and figures out the
230 * slot on Bus 0 where this device eventually hooks to. 230 * slot on Bus 0 where this device eventually hooks to.
231 * @pin: The PCI interrupt pin read from the device, then swizzled 231 * @pin: The PCI interrupt pin read from the device, then swizzled
232 * as it goes through each bridge. 232 * as it goes through each bridge.
233 * Returns Interrupt number for the device 233 * Returns Interrupt number for the device
234 */ 234 */
235int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, 235int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
@@ -404,8 +404,8 @@ static void octeon_pci_initialize(void)
404 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ 404 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
405 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ 405 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
406 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ 406 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
407 ctl_status_2.s.bb1 = 1; /* BAR1 is big */ 407 ctl_status_2.s.bb1 = 1; /* BAR1 is big */
408 ctl_status_2.s.bb0 = 1; /* BAR0 is big */ 408 ctl_status_2.s.bb0 = 1; /* BAR0 is big */
409 } 409 }
410 410
411 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); 411 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
@@ -446,7 +446,7 @@ static void octeon_pci_initialize(void)
446 * count. [1..31] and 0=32. NOTE: If the user 446 * count. [1..31] and 0=32. NOTE: If the user
447 * programs these bits beyond the Designed Maximum 447 * programs these bits beyond the Designed Maximum
448 * outstanding count, then the designed maximum table 448 * outstanding count, then the designed maximum table
449 * depth will be used instead. No additional 449 * depth will be used instead. No additional
450 * Deferred/Split transactions will be accepted if 450 * Deferred/Split transactions will be accepted if
451 * this outstanding maximum count is 451 * this outstanding maximum count is
452 * reached. Furthermore, no additional deferred/split 452 * reached. Furthermore, no additional deferred/split
@@ -456,7 +456,7 @@ static void octeon_pci_initialize(void)
456 cfg19.s.tdomc = 4; 456 cfg19.s.tdomc = 4;
457 /* 457 /*
458 * Master Deferred Read Request Outstanding Max Count 458 * Master Deferred Read Request Outstanding Max Count
459 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC 459 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
460 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 460 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
461 * 5 2 110 6 3 111 7 3 For example, if these bits are 461 * 5 2 110 6 3 111 7 3 For example, if these bits are
462 * programmed to 100, the core can support 2 DAC 462 * programmed to 100, the core can support 2 DAC
@@ -550,7 +550,7 @@ static void octeon_pci_initialize(void)
550 550
551 /* 551 /*
552 * Affects PCI performance when OCTEON services reads to its 552 * Affects PCI performance when OCTEON services reads to its
553 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are 553 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
554 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and 554 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
555 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, 555 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
556 * these values need to be changed so they won't possibly prefetch off 556 * these values need to be changed so they won't possibly prefetch off
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index 5f3a69cebad1..b128cb973ebe 100644
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -33,7 +33,7 @@
33#include <asm/mach-rc32434/rc32434.h> 33#include <asm/mach-rc32434/rc32434.h>
34#include <asm/mach-rc32434/pci.h> 34#include <asm/mach-rc32434/pci.h>
35 35
36#define PCI_ACCESS_READ 0 36#define PCI_ACCESS_READ 0
37#define PCI_ACCESS_WRITE 1 37#define PCI_ACCESS_WRITE 1
38 38
39/* define an unsigned array for the PCI registers */ 39/* define an unsigned array for the PCI registers */
@@ -82,11 +82,11 @@ extern struct pci_ops rc32434_pci_ops;
82#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN) 82#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
83#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1) 83#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
84#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)) 84#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
85#define PCI_IO1_END \ 85#define PCI_IO1_END \
86 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1) 86 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
87#define PCI_IO2_START \ 87#define PCI_IO2_START \
88 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN) 88 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
89#define PCI_IO2_END \ 89#define PCI_IO2_END \
90 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1) 90 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
91 91
92struct pci_controller rc32434_controller2; 92struct pci_controller rc32434_controller2;
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index dd97f3a83baa..cdefcc4cb8d4 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -55,9 +55,9 @@
55 55
56static void *cfg_space; 56static void *cfg_space;
57 57
58#define PCI_BUS_ENABLED 1 58#define PCI_BUS_ENABLED 1
59#define LDT_BUS_ENABLED 2 59#define LDT_BUS_ENABLED 2
60#define PCI_DEVICE_MODE 4 60#define PCI_DEVICE_MODE 4
61 61
62static int sb1250_bus_status; 62static int sb1250_bus_status;
63 63
@@ -239,7 +239,7 @@ static int __init sb1250_pcibios_init(void)
239 PCI_COMMAND)); 239 PCI_COMMAND));
240 if (!(cmdreg & PCI_COMMAND_MASTER)) { 240 if (!(cmdreg & PCI_COMMAND_MASTER)) {
241 printk 241 printk
242 ("PCI: Skipping PCI probe. Bus is not initialized.\n"); 242 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
243 iounmap(cfg_space); 243 iounmap(cfg_space);
244 return 0; 244 return 0;
245 } 245 }
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 444b8d8004ad..157c7715b7c8 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -69,17 +69,17 @@ static struct pci_target_address_window pci_target_window1 = {
69}; 69};
70 70
71static struct resource pci_mem_resource = { 71static struct resource pci_mem_resource = {
72 .name = "PCI Memory resources", 72 .name = "PCI Memory resources",
73 .start = PCI_MEM_RESOURCE_START, 73 .start = PCI_MEM_RESOURCE_START,
74 .end = PCI_MEM_RESOURCE_END, 74 .end = PCI_MEM_RESOURCE_END,
75 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
76}; 76};
77 77
78static struct resource pci_io_resource = { 78static struct resource pci_io_resource = {
79 .name = "PCI I/O resources", 79 .name = "PCI I/O resources",
80 .start = PCI_IO_RESOURCE_START, 80 .start = PCI_IO_RESOURCE_START,
81 .end = PCI_IO_RESOURCE_END, 81 .end = PCI_IO_RESOURCE_END,
82 .flags = IORESOURCE_IO, 82 .flags = IORESOURCE_IO,
83}; 83};
84 84
85static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = { 85static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
@@ -97,7 +97,7 @@ static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
97}; 97};
98 98
99static struct pci_controller vr41xx_pci_controller = { 99static struct pci_controller vr41xx_pci_controller = {
100 .pci_ops = &vr41xx_pci_ops, 100 .pci_ops = &vr41xx_pci_ops,
101 .mem_resource = &pci_mem_resource, 101 .mem_resource = &pci_mem_resource,
102 .io_resource = &pci_io_resource, 102 .io_resource = &pci_io_resource,
103}; 103};
@@ -148,7 +148,7 @@ static int __init vr41xx_pciu_init(void)
148 else if ((vtclock / 2) < pci_clock_max) 148 else if ((vtclock / 2) < pci_clock_max)
149 pciu_write(PCICLKSELREG, HALF_VTCLOCK); 149 pciu_write(PCICLKSELREG, HALF_VTCLOCK);
150 else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 && 150 else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
151 (vtclock / 3) < pci_clock_max) 151 (vtclock / 3) < pci_clock_max)
152 pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK); 152 pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
153 else if ((vtclock / 4) < pci_clock_max) 153 else if ((vtclock / 4) < pci_clock_max)
154 pciu_write(PCICLKSELREG, QUARTER_VTCLOCK); 154 pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
@@ -281,7 +281,7 @@ static int __init vr41xx_pciu_init(void)
281 pciu_write(PCIAPCNTREG, val); 281 pciu_write(PCIAPCNTREG, val);
282 282
283 pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 283 pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
284 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | 284 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
285 PCI_COMMAND_SERR); 285 PCI_COMMAND_SERR);
286 286
287 /* Clear bus error */ 287 /* Clear bus error */
diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h
index 6b1ae2eb1c06..e6b4a1b969f7 100644
--- a/arch/mips/pci/pci-vr41xx.h
+++ b/arch/mips/pci/pci-vr41xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series. 2 * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
3 * 3 *
4 * Copyright (C) 2002 MontaVista Software Inc. 4 * Copyright (C) 2002 MontaVista Software Inc.
5 * Author: Yoichi Yuasa <source@mvista.com> 5 * Author: Yoichi Yuasa <source@mvista.com>
6 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org> 6 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
7 * 7 *
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index 140557a20488..ad55f2cfeec1 100644
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -55,7 +55,7 @@
55 55
56static void *pci_config_base; 56static void *pci_config_base;
57 57
58#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) 58#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
59 59
60/* PCI ops */ 60/* PCI ops */
61static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, 61static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
@@ -135,26 +135,26 @@ struct pci_ops nlm_pci_ops = {
135}; 135};
136 136
137static struct resource nlm_pci_mem_resource = { 137static struct resource nlm_pci_mem_resource = {
138 .name = "XLP PCI MEM", 138 .name = "XLP PCI MEM",
139 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ 139 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
140 .end = 0xdfffffffUL, 140 .end = 0xdfffffffUL,
141 .flags = IORESOURCE_MEM, 141 .flags = IORESOURCE_MEM,
142}; 142};
143 143
144static struct resource nlm_pci_io_resource = { 144static struct resource nlm_pci_io_resource = {
145 .name = "XLP IO MEM", 145 .name = "XLP IO MEM",
146 .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */ 146 .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
147 .end = 0x17ffffffUL, 147 .end = 0x17ffffffUL,
148 .flags = IORESOURCE_IO, 148 .flags = IORESOURCE_IO,
149}; 149};
150 150
151struct pci_controller nlm_pci_controller = { 151struct pci_controller nlm_pci_controller = {
152 .index = 0, 152 .index = 0,
153 .pci_ops = &nlm_pci_ops, 153 .pci_ops = &nlm_pci_ops,
154 .mem_resource = &nlm_pci_mem_resource, 154 .mem_resource = &nlm_pci_mem_resource,
155 .mem_offset = 0x00000000UL, 155 .mem_offset = 0x00000000UL,
156 .io_resource = &nlm_pci_io_resource, 156 .io_resource = &nlm_pci_io_resource,
157 .io_offset = 0x00000000UL, 157 .io_offset = 0x00000000UL,
158}; 158};
159 159
160static int get_irq_vector(const struct pci_dev *dev) 160static int get_irq_vector(const struct pci_dev *dev)
@@ -232,7 +232,7 @@ static int __init pcibios_init(void)
232 pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); 232 pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
233 233
234 /* Extend IO port for memory mapped io */ 234 /* Extend IO port for memory mapped io */
235 ioport_resource.start = 0; 235 ioport_resource.start = 0;
236 ioport_resource.end = ~0; 236 ioport_resource.end = ~0;
237 237
238 xlp_enable_pci_bswap(); 238 xlp_enable_pci_bswap();
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 0c18ccc79623..4427abbd48b5 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -56,7 +56,7 @@
56 56
57static void *pci_config_base; 57static void *pci_config_base;
58 58
59#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) 59#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
60 60
61/* PCI ops */ 61/* PCI ops */
62static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, 62static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
@@ -136,26 +136,26 @@ struct pci_ops nlm_pci_ops = {
136}; 136};
137 137
138static struct resource nlm_pci_mem_resource = { 138static struct resource nlm_pci_mem_resource = {
139 .name = "XLR PCI MEM", 139 .name = "XLR PCI MEM",
140 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ 140 .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
141 .end = 0xdfffffffUL, 141 .end = 0xdfffffffUL,
142 .flags = IORESOURCE_MEM, 142 .flags = IORESOURCE_MEM,
143}; 143};
144 144
145static struct resource nlm_pci_io_resource = { 145static struct resource nlm_pci_io_resource = {
146 .name = "XLR IO MEM", 146 .name = "XLR IO MEM",
147 .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ 147 .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
148 .end = 0x100fffffUL, 148 .end = 0x100fffffUL,
149 .flags = IORESOURCE_IO, 149 .flags = IORESOURCE_IO,
150}; 150};
151 151
152struct pci_controller nlm_pci_controller = { 152struct pci_controller nlm_pci_controller = {
153 .index = 0, 153 .index = 0,
154 .pci_ops = &nlm_pci_ops, 154 .pci_ops = &nlm_pci_ops,
155 .mem_resource = &nlm_pci_mem_resource, 155 .mem_resource = &nlm_pci_mem_resource,
156 .mem_offset = 0x00000000UL, 156 .mem_offset = 0x00000000UL,
157 .io_resource = &nlm_pci_io_resource, 157 .io_resource = &nlm_pci_io_resource,
158 .io_offset = 0x00000000UL, 158 .io_offset = 0x00000000UL,
159}; 159};
160 160
161/* 161/*
@@ -259,7 +259,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
259 MSI_ADDR_REDIRECTION_CPU; 259 MSI_ADDR_REDIRECTION_CPU;
260 260
261 msg.data = MSI_DATA_TRIGGER_EDGE | 261 msg.data = MSI_DATA_TRIGGER_EDGE |
262 MSI_DATA_LEVEL_ASSERT | 262 MSI_DATA_LEVEL_ASSERT |
263 MSI_DATA_DELIVERY_FIXED; 263 MSI_DATA_DELIVERY_FIXED;
264 264
265 ret = irq_set_msi_desc(irq, desc); 265 ret = irq_set_msi_desc(irq, desc);
@@ -344,7 +344,7 @@ static int __init pcibios_init(void)
344 pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); 344 pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
345 345
346 /* Extend IO port for memory mapped io */ 346 /* Extend IO port for memory mapped io */
347 ioport_resource.start = 0; 347 ioport_resource.start = 0;
348 ioport_resource.end = ~0; 348 ioport_resource.end = ~0;
349 349
350 set_io_port_base(CKSEG1); 350 set_io_port_base(CKSEG1);
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index a1843448fad3..e8a14a6514cf 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * This program is free software; you can redistribute it and/or modify it 2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the 3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your 4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version. 5 * option) any later version.
6 * 6 *
diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index fdb4d558c0cc..5e36c33e5543 100644
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -43,7 +43,7 @@ union cvmx_pcie_address {
43 uint64_t upper:2; /* Normally 2 for XKPHYS */ 43 uint64_t upper:2; /* Normally 2 for XKPHYS */
44 uint64_t reserved_49_61:13; /* Must be zero */ 44 uint64_t reserved_49_61:13; /* Must be zero */
45 uint64_t io:1; /* 1 for IO space access */ 45 uint64_t io:1; /* 1 for IO space access */
46 uint64_t did:5; /* PCIe DID = 3 */ 46 uint64_t did:5; /* PCIe DID = 3 */
47 uint64_t subdid:3; /* PCIe SubDID = 1 */ 47 uint64_t subdid:3; /* PCIe SubDID = 1 */
48 uint64_t reserved_36_39:4; /* Must be zero */ 48 uint64_t reserved_36_39:4; /* Must be zero */
49 uint64_t es:2; /* Endian swap = 1 */ 49 uint64_t es:2; /* Endian swap = 1 */
@@ -74,7 +74,7 @@ union cvmx_pcie_address {
74 uint64_t upper:2; /* Normally 2 for XKPHYS */ 74 uint64_t upper:2; /* Normally 2 for XKPHYS */
75 uint64_t reserved_49_61:13; /* Must be zero */ 75 uint64_t reserved_49_61:13; /* Must be zero */
76 uint64_t io:1; /* 1 for IO space access */ 76 uint64_t io:1; /* 1 for IO space access */
77 uint64_t did:5; /* PCIe DID = 3 */ 77 uint64_t did:5; /* PCIe DID = 3 */
78 uint64_t subdid:3; /* PCIe SubDID = 2 */ 78 uint64_t subdid:3; /* PCIe SubDID = 2 */
79 uint64_t reserved_36_39:4; /* Must be zero */ 79 uint64_t reserved_36_39:4; /* Must be zero */
80 uint64_t es:2; /* Endian swap = 1 */ 80 uint64_t es:2; /* Endian swap = 1 */
@@ -85,7 +85,7 @@ union cvmx_pcie_address {
85 uint64_t upper:2; /* Normally 2 for XKPHYS */ 85 uint64_t upper:2; /* Normally 2 for XKPHYS */
86 uint64_t reserved_49_61:13; /* Must be zero */ 86 uint64_t reserved_49_61:13; /* Must be zero */
87 uint64_t io:1; /* 1 for IO space access */ 87 uint64_t io:1; /* 1 for IO space access */
88 uint64_t did:5; /* PCIe DID = 3 */ 88 uint64_t did:5; /* PCIe DID = 3 */
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */ 89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
90 uint64_t reserved_36_39:4; /* Must be zero */ 90 uint64_t reserved_36_39:4; /* Must be zero */
91 uint64_t address:36; /* PCIe Mem address */ 91 uint64_t address:36; /* PCIe Mem address */
@@ -166,7 +166,7 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
166 * Read a PCIe config space register indirectly. This is used for 166 * Read a PCIe config space register indirectly. This is used for
167 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. 167 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
168 * 168 *
169 * @pcie_port: PCIe port to read from 169 * @pcie_port: PCIe port to read from
170 * @cfg_offset: Address to read 170 * @cfg_offset: Address to read
171 * 171 *
172 * Returns Value read 172 * Returns Value read
@@ -194,9 +194,9 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
194 * Write a PCIe config space register indirectly. This is used for 194 * Write a PCIe config space register indirectly. This is used for
195 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???. 195 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
196 * 196 *
197 * @pcie_port: PCIe port to write to 197 * @pcie_port: PCIe port to write to
198 * @cfg_offset: Address to write 198 * @cfg_offset: Address to write
199 * @val: Value to write 199 * @val: Value to write
200 */ 200 */
201static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, 201static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
202 uint32_t val) 202 uint32_t val)
@@ -222,7 +222,7 @@ static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
222 * @pcie_port: PCIe port to access 222 * @pcie_port: PCIe port to access
223 * @bus: Sub bus 223 * @bus: Sub bus
224 * @dev: Device ID 224 * @dev: Device ID
225 * @fn: Device sub function 225 * @fn: Device sub function
226 * @reg: Register to access 226 * @reg: Register to access
227 * 227 *
228 * Returns 64bit Octeon IO address 228 * Returns 64bit Octeon IO address
@@ -259,7 +259,7 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
259 * @pcie_port: PCIe port the device is on 259 * @pcie_port: PCIe port the device is on
260 * @bus: Sub bus 260 * @bus: Sub bus
261 * @dev: Device ID 261 * @dev: Device ID
262 * @fn: Device sub function 262 * @fn: Device sub function
263 * @reg: Register to access 263 * @reg: Register to access
264 * 264 *
265 * Returns Result of the read 265 * Returns Result of the read
@@ -281,7 +281,7 @@ static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
281 * @pcie_port: PCIe port the device is on 281 * @pcie_port: PCIe port the device is on
282 * @bus: Sub bus 282 * @bus: Sub bus
283 * @dev: Device ID 283 * @dev: Device ID
284 * @fn: Device sub function 284 * @fn: Device sub function
285 * @reg: Register to access 285 * @reg: Register to access
286 * 286 *
287 * Returns Result of the read 287 * Returns Result of the read
@@ -303,7 +303,7 @@ static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
303 * @pcie_port: PCIe port the device is on 303 * @pcie_port: PCIe port the device is on
304 * @bus: Sub bus 304 * @bus: Sub bus
305 * @dev: Device ID 305 * @dev: Device ID
306 * @fn: Device sub function 306 * @fn: Device sub function
307 * @reg: Register to access 307 * @reg: Register to access
308 * 308 *
309 * Returns Result of the read 309 * Returns Result of the read
@@ -325,7 +325,7 @@ static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
325 * @pcie_port: PCIe port the device is on 325 * @pcie_port: PCIe port the device is on
326 * @bus: Sub bus 326 * @bus: Sub bus
327 * @dev: Device ID 327 * @dev: Device ID
328 * @fn: Device sub function 328 * @fn: Device sub function
329 * @reg: Register to access 329 * @reg: Register to access
330 * @val: Value to write 330 * @val: Value to write
331 */ 331 */
@@ -344,7 +344,7 @@ static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
344 * @pcie_port: PCIe port the device is on 344 * @pcie_port: PCIe port the device is on
345 * @bus: Sub bus 345 * @bus: Sub bus
346 * @dev: Device ID 346 * @dev: Device ID
347 * @fn: Device sub function 347 * @fn: Device sub function
348 * @reg: Register to access 348 * @reg: Register to access
349 * @val: Value to write 349 * @val: Value to write
350 */ 350 */
@@ -363,7 +363,7 @@ static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
363 * @pcie_port: PCIe port the device is on 363 * @pcie_port: PCIe port the device is on
364 * @bus: Sub bus 364 * @bus: Sub bus
365 * @dev: Device ID 365 * @dev: Device ID
366 * @fn: Device sub function 366 * @fn: Device sub function
367 * @reg: Register to access 367 * @reg: Register to access
368 * @val: Value to write 368 * @val: Value to write
369 */ 369 */
@@ -883,14 +883,14 @@ retry:
883 883
884 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */ 884 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
885 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL); 885 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
886 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */ 886 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
887 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */ 887 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
888 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64); 888 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
889 889
890 /* Setup Mem access SubDIDs */ 890 /* Setup Mem access SubDIDs */
891 mem_access_subid.u64 = 0; 891 mem_access_subid.u64 = 0;
892 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ 892 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
893 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */ 893 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
894 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ 894 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
895 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ 895 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
896 mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */ 896 mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
@@ -926,7 +926,7 @@ retry:
926 926
927 bar1_index.u32 = 0; 927 bar1_index.u32 = 0;
928 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); 928 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
929 bar1_index.s.ca = 1; /* Not Cached */ 929 bar1_index.s.ca = 1; /* Not Cached */
930 bar1_index.s.end_swp = 1; /* Endian Swap mode */ 930 bar1_index.s.end_swp = 1; /* Endian Swap mode */
931 bar1_index.s.addr_v = 1; /* Valid entry */ 931 bar1_index.s.addr_v = 1; /* Valid entry */
932 932
@@ -1342,11 +1342,11 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1342 /* Setup Mem access SubDIDs */ 1342 /* Setup Mem access SubDIDs */
1343 mem_access_subid.u64 = 0; 1343 mem_access_subid.u64 = 0;
1344 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */ 1344 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1345 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */ 1345 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
1346 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ 1346 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
1347 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ 1347 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
1348 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ 1348 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1349 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */ 1349 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1350 /* PCIe Adddress Bits <63:34>. */ 1350 /* PCIe Adddress Bits <63:34>. */
1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1352 mem_access_subid.cn68xx.ba = 0; 1352 mem_access_subid.cn68xx.ba = 0;
@@ -1409,7 +1409,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1409 1409
1410 bar1_index.u64 = 0; 1410 bar1_index.u64 = 0;
1411 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22); 1411 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1412 bar1_index.s.ca = 1; /* Not Cached */ 1412 bar1_index.s.ca = 1; /* Not Cached */
1413 bar1_index.s.end_swp = 1; /* Endian Swap mode */ 1413 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1414 bar1_index.s.addr_v = 1; /* Valid entry */ 1414 bar1_index.s.addr_v = 1; /* Valid entry */
1415 1415
@@ -1458,10 +1458,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
1458 * 1458 *
1459 * @dev: The Linux PCI device structure for the device to map 1459 * @dev: The Linux PCI device structure for the device to map
1460 * @slot: The slot number for this device on __BUS 0__. Linux 1460 * @slot: The slot number for this device on __BUS 0__. Linux
1461 * enumerates through all the bridges and figures out the 1461 * enumerates through all the bridges and figures out the
1462 * slot on Bus 0 where this device eventually hooks to. 1462 * slot on Bus 0 where this device eventually hooks to.
1463 * @pin: The PCI interrupt pin read from the device, then swizzled 1463 * @pin: The PCI interrupt pin read from the device, then swizzled
1464 * as it goes through each bridge. 1464 * as it goes through each bridge.
1465 * Returns Interrupt number for the device 1465 * Returns Interrupt number for the device
1466 */ 1466 */
1467int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev, 1467int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
@@ -1503,7 +1503,7 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1503 return pin - 1 + OCTEON_IRQ_PCI_INT0; 1503 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1504} 1504}
1505 1505
1506static void set_cfg_read_retry(u32 retry_cnt) 1506static void set_cfg_read_retry(u32 retry_cnt)
1507{ 1507{
1508 union cvmx_pemx_ctl_status pemx_ctl; 1508 union cvmx_pemx_ctl_status pemx_ctl;
1509 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1)); 1509 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
@@ -1931,7 +1931,7 @@ static int __init octeon_pcie_setup(void)
1931 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { 1931 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1932 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0)); 1932 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
1933 if (sriox_status_reg.s.srio) { 1933 if (sriox_status_reg.s.srio) {
1934 srio_war15205 += 1; /* Port is SRIO */ 1934 srio_war15205 += 1; /* Port is SRIO */
1935 port = 0; 1935 port = 0;
1936 } 1936 }
1937 } 1937 }
@@ -2004,7 +2004,7 @@ static int __init octeon_pcie_setup(void)
2004 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) { 2004 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2005 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1)); 2005 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
2006 if (sriox_status_reg.s.srio) { 2006 if (sriox_status_reg.s.srio) {
2007 srio_war15205 += 1; /* Port is SRIO */ 2007 srio_war15205 += 1; /* Port is SRIO */
2008 port = 1; 2008 port = 1;
2009 } 2009 }
2010 } 2010 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 21:35:35 -0500