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authorRalf Baechle <ralf@linux-mips.org>2008-07-16 11:12:25 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-20 09:38:18 -0400
commit73b4390fb23456964201abda79f1210fe337d01a (patch)
treebc613dfa0a3926bd889025cebbc28ae034b8c854 /arch/mips/pci
parent36a0a3cd45b49ceff78ac28efef1cbeec413d8c2 (diff)
[MIPS] Routerboard 532: Support for base system
Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-rc32434.c69
-rw-r--r--arch/mips/pci/ops-rc32434.c207
-rw-r--r--arch/mips/pci/pci-rc32434.c221
4 files changed, 498 insertions, 0 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 57e34cafa497..15e01aec37fd 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
52obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
new file mode 100644
index 000000000000..75b90dcb7a09
--- /dev/null
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * stevel@mvista.com or source@mvista.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/types.h>
28#include <linux/pci.h>
29#include <linux/kernel.h>
30#include <linux/init.h>
31
32#include <asm/mach-rc32434/rc32434.h>
33
34static int __devinitdata irq_map[2][12] = {
35 {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
36 {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3}
37};
38
39int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
40{
41 int irq = 0;
42
43 if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12)
44 irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
45
46 return irq + GROUP4_IRQ_BASE + 4;
47}
48
49static void rc32434_pci_early_fixup(struct pci_dev *dev)
50{
51 if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
52 /* disable prefetched memory range */
53 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
54 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
55
56 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
57 }
58}
59
60/*
61 * The fixup applies to both the IDT and VIA devices present on the board
62 */
63DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, rc32434_pci_early_fixup);
64
65/* Do platform specific device initialization at pci_enable_device() time */
66int pcibios_plat_dev_init(struct pci_dev *dev)
67{
68 return 0;
69}
diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
new file mode 100644
index 000000000000..d1f8fa210ca1
--- /dev/null
+++ b/arch/mips/pci/ops-rc32434.c
@@ -0,0 +1,207 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * pci_ops for IDT EB434 board
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 * Copyright 2006 Felix Fietkau <nbd@openwrt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#include <linux/delay.h>
29#include <linux/init.h>
30#include <linux/io.h>
31#include <linux/pci.h>
32#include <linux/types.h>
33
34#include <asm/cpu.h>
35#include <asm/mach-rc32434/rc32434.h>
36#include <asm/mach-rc32434/pci.h>
37
38#define PCI_ACCESS_READ 0
39#define PCI_ACCESS_WRITE 1
40
41
42#define PCI_CFG_SET(bus, slot, func, off) \
43 (rc32434_pci->pcicfga = (0x80000000 | \
44 ((bus) << 16) | ((slot)<<11) | \
45 ((func)<<8) | (off)))
46
47static inline int config_access(unsigned char access_type,
48 struct pci_bus *bus, unsigned int devfn,
49 unsigned char where, u32 *data)
50{
51 unsigned int slot = PCI_SLOT(devfn);
52 u8 func = PCI_FUNC(devfn);
53
54 /* Setup address */
55 PCI_CFG_SET(bus->number, slot, func, where);
56 rc32434_sync();
57
58 if (access_type == PCI_ACCESS_WRITE)
59 rc32434_pci->pcicfgd = *data;
60 else
61 *data = rc32434_pci->pcicfgd;
62
63 rc32434_sync();
64
65 return 0;
66}
67
68
69/*
70 * We can't address 8 and 16 bit words directly. Instead we have to
71 * read/write a 32bit word and mask/modify the data we actually want.
72 */
73static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
74 int where, u8 *val)
75{
76 u32 data;
77 int ret;
78
79 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
80 *val = (data >> ((where & 3) << 3)) & 0xff;
81 return ret;
82}
83
84static int read_config_word(struct pci_bus *bus, unsigned int devfn,
85 int where, u16 *val)
86{
87 u32 data;
88 int ret;
89
90 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
91 *val = (data >> ((where & 3) << 3)) & 0xffff;
92 return ret;
93}
94
95static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
96 int where, u32 *val)
97{
98 int ret;
99 int delay = 1;
100
101 /*
102 * Don't scan too far, else there will be errors with plugged in
103 * daughterboard (rb564).
104 */
105 if (bus->number == 0 && PCI_SLOT(devfn) > 21)
106 return 0;
107
108retry:
109 ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
110
111 /*
112 * Certain devices react delayed at device scan time, this
113 * gives them time to settle
114 */
115 if (where == PCI_VENDOR_ID) {
116 if (ret == 0xffffffff || ret == 0x00000000 ||
117 ret == 0x0000ffff || ret == 0xffff0000) {
118 if (delay > 4)
119 return 0;
120 delay *= 2;
121 msleep(delay);
122 goto retry;
123 }
124 }
125
126 return ret;
127}
128
129static int
130write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
131 u8 val)
132{
133 u32 data = 0;
134
135 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
136 return -1;
137
138 data = (data & ~(0xff << ((where & 3) << 3))) |
139 (val << ((where & 3) << 3));
140
141 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
142 return -1;
143
144 return PCIBIOS_SUCCESSFUL;
145}
146
147
148static int
149write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
150 u16 val)
151{
152 u32 data = 0;
153
154 if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
155 return -1;
156
157 data = (data & ~(0xffff << ((where & 3) << 3))) |
158 (val << ((where & 3) << 3));
159
160 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
161 return -1;
162
163
164 return PCIBIOS_SUCCESSFUL;
165}
166
167
168static int
169write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
170 u32 val)
171{
172 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
173 return -1;
174
175 return PCIBIOS_SUCCESSFUL;
176}
177
178static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
179 int where, int size, u32 *val)
180{
181 switch (size) {
182 case 1:
183 return read_config_byte(bus, devfn, where, (u8 *) val);
184 case 2:
185 return read_config_word(bus, devfn, where, (u16 *) val);
186 default:
187 return read_config_dword(bus, devfn, where, val);
188 }
189}
190
191static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
192 int where, int size, u32 val)
193{
194 switch (size) {
195 case 1:
196 return write_config_byte(bus, devfn, where, (u8) val);
197 case 2:
198 return write_config_word(bus, devfn, where, (u16) val);
199 default:
200 return write_config_dword(bus, devfn, where, val);
201 }
202}
203
204struct pci_ops rc32434_pci_ops = {
205 .read = pci_config_read,
206 .write = pci_config_write,
207};
diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
new file mode 100644
index 000000000000..1c2821e2f494
--- /dev/null
+++ b/arch/mips/pci/pci-rc32434.c
@@ -0,0 +1,221 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PCI initialization for IDT EB434 board
4 *
5 * Copyright 2004 IDT Inc. (rischelp@idt.com)
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/types.h>
29#include <linux/pci.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32
33#include <asm/mach-rc32434/rc32434.h>
34#include <asm/mach-rc32434/pci.h>
35
36#define PCI_ACCESS_READ 0
37#define PCI_ACCESS_WRITE 1
38
39/* define an unsigned array for the PCI registers */
40static unsigned int korina_cnfg_regs[25] = {
41 KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
42 KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
43 KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
44 KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
45 KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
46 KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
47};
48static struct resource rc32434_res_pci_mem1;
49static struct resource rc32434_res_pci_mem2;
50
51static struct resource rc32434_res_pci_mem1 = {
52 .name = "PCI MEM1",
53 .start = 0x50000000,
54 .end = 0x5FFFFFFF,
55 .flags = IORESOURCE_MEM,
56 .parent = &rc32434_res_pci_mem1,
57 .sibling = NULL,
58 .child = &rc32434_res_pci_mem2
59};
60
61static struct resource rc32434_res_pci_mem2 = {
62 .name = "PCI Mem2",
63 .start = 0x60000000,
64 .end = 0x6FFFFFFF,
65 .flags = IORESOURCE_MEM,
66 .parent = &rc32434_res_pci_mem1,
67 .sibling = NULL,
68 .child = NULL
69};
70
71static struct resource rc32434_res_pci_io1 = {
72 .name = "PCI I/O1",
73 .start = 0x18800000,
74 .end = 0x188FFFFF,
75 .flags = IORESOURCE_IO,
76};
77
78extern struct pci_ops rc32434_pci_ops;
79
80#define PCI_MEM1_START PCI_ADDR_START
81#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1)
82#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
83#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1)
84#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
85#define PCI_IO1_END \
86 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
87#define PCI_IO2_START \
88 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
89#define PCI_IO2_END \
90 (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
91
92struct pci_controller rc32434_controller2;
93
94struct pci_controller rc32434_controller = {
95 .pci_ops = &rc32434_pci_ops,
96 .mem_resource = &rc32434_res_pci_mem1,
97 .io_resource = &rc32434_res_pci_io1,
98 .mem_offset = 0,
99 .io_offset = 0,
100
101};
102
103#ifdef __MIPSEB__
104#define PCI_ENDIAN_FLAG PCILBAC_sb_m
105#else
106#define PCI_ENDIAN_FLAG 0
107#endif
108
109static int __init rc32434_pcibridge_init(void)
110{
111 unsigned int pcicvalue, pcicdata = 0;
112 unsigned int dummyread, pcicntlval;
113 int loopCount;
114 unsigned int pci_config_addr;
115
116 pcicvalue = rc32434_pci->pcic;
117 pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN;
118 if (!((pcicvalue == PCIM_H_EA) ||
119 (pcicvalue == PCIM_H_IA_FIX) ||
120 (pcicvalue == PCIM_H_IA_RR))) {
121 pr_err(KERN_ERR "PCI init error!!!\n");
122 /* Not in Host Mode, return ERROR */
123 return -1;
124 }
125 /* Enables the Idle Grant mode, Arbiter Parking */
126 pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN);
127 rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */
128 /* Zero out the PCI status & PCI Status Mask */
129 for (;;) {
130 pcicdata = rc32434_pci->pcis;
131 if (!(pcicdata & PCI_STAT_RIP))
132 break;
133 }
134
135 rc32434_pci->pcis = 0;
136 rc32434_pci->pcism = 0xFFFFFFFF;
137 /* Zero out the PCI decoupled registers */
138 rc32434_pci->pcidac = 0; /*
139 * disable PCI decoupled accesses at
140 * initialization
141 */
142 rc32434_pci->pcidas = 0; /* clear the status */
143 rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */
144 /* Mask PCI Messaging Interrupts */
145 rc32434_pci_msg->pciiic = 0;
146 rc32434_pci_msg->pciiim = 0xFFFFFFFF;
147 rc32434_pci_msg->pciioic = 0;
148 rc32434_pci_msg->pciioim = 0;
149
150
151 /* Setup PCILB0 as Memory Window */
152 rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START);
153
154 /* setup the PCI map address as same as the local address */
155
156 rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START);
157
158
159 /* Setup PCILBA1 as MEM */
160 rc32434_pci->pcilba[0].control =
161 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
162 dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */
163 rc32434_pci->pcilba[1].address = 0x60000000;
164 rc32434_pci->pcilba[1].mapping = 0x60000000;
165
166 /* setup PCILBA2 as IO Window */
167 rc32434_pci->pcilba[1].control =
168 (((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
169 dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */
170 rc32434_pci->pcilba[2].address = 0x18C00000;
171 rc32434_pci->pcilba[2].mapping = 0x18FFFFFF;
172
173 /* setup PCILBA2 as IO Window */
174 rc32434_pci->pcilba[2].control =
175 (((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG);
176 dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */
177
178 /* Setup PCILBA3 as IO Window */
179 rc32434_pci->pcilba[3].address = 0x18800000;
180 rc32434_pci->pcilba[3].mapping = 0x18800000;
181 rc32434_pci->pcilba[3].control =
182 ((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) |
183 PCI_ENDIAN_FLAG);
184 dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */
185
186 pci_config_addr = (unsigned int) (0x80000004);
187 for (loopCount = 0; loopCount < 24; loopCount++) {
188 rc32434_pci->pcicfga = pci_config_addr;
189 dummyread = rc32434_pci->pcicfga;
190 rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount];
191 dummyread = rc32434_pci->pcicfgd;
192 pci_config_addr += 4;
193 }
194 rc32434_pci->pcitc =
195 (unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) |
196 ((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT);
197
198 pcicntlval = rc32434_pci->pcic;
199 pcicntlval &= ~PCI_CTL_TNR;
200 rc32434_pci->pcic = pcicntlval;
201 pcicntlval = rc32434_pci->pcic;
202
203 return 0;
204}
205
206static int __init rc32434_pci_init(void)
207{
208 pr_info("PCI: Initializing PCI\n");
209
210 ioport_resource.start = rc32434_res_pci_io1.start;
211 ioport_resource.end = rc32434_res_pci_io1.end;
212
213 rc32434_pcibridge_init();
214
215 register_pci_controller(&rc32434_controller);
216 rc32434_sync();
217
218 return 0;
219}
220
221arch_initcall(rc32434_pci_init);
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