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authorRalf Baechle <ralf@linux-mips.org>2006-06-17 23:58:57 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-19 12:39:24 -0400
commiteaff3888742155bd397e45a1c3323c0173042e5b (patch)
treebf8ee6203072e01ce0d50db5898137c7552da6e5 /arch/mips/pci
parent2925aba4223f4532e85f0c6f64584b3e0b2849c3 (diff)
[MIPS] Remove support for NEC DDB5074.
As warned several times before. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-ddb5074.c21
-rw-r--r--arch/mips/pci/ops-ddb5074.c271
-rw-r--r--arch/mips/pci/pci-ddb5074.c79
4 files changed, 0 insertions, 372 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bb6b6226a57a..d028197d8326 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -22,7 +22,6 @@ obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
22# 22#
23# These are still pretty much in the old state, watch, go blind. 23# These are still pretty much in the old state, watch, go blind.
24# 24#
25obj-$(CONFIG_DDB5074) += fixup-ddb5074.o pci-ddb5074.o ops-ddb5074.o
26obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o 25obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o
27obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o 26obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
28obj-$(CONFIG_LASAT) += pci-lasat.o 27obj-$(CONFIG_LASAT) += pci-lasat.o
diff --git a/arch/mips/pci/fixup-ddb5074.c b/arch/mips/pci/fixup-ddb5074.c
deleted file mode 100644
index 5a4a7c239c42..000000000000
--- a/arch/mips/pci/fixup-ddb5074.c
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * It's nice to have the LEDs on the GPIO pins available for debugging
3 */
4static void ddb5074_fixup(struct pci_dev *dev)
5{
6 extern struct pci_dev *pci_pmu;
7 u8 t8;
8
9 pci_pmu = dev; /* for LEDs D2 and D3 */
10 /* Program the lines for LEDs D2 and D3 to output */
11 pci_read_config_byte(dev, 0x7d, &t8);
12 t8 |= 0xc0;
13 pci_write_config_byte(dev, 0x7d, t8);
14 /* Turn LEDs D2 and D3 off */
15 pci_read_config_byte(dev, 0x7e, &t8);
16 t8 |= 0xc0;
17 pci_write_config_byte(dev, 0x7e, t8);
18}
19
20DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101,
21 ddb5074_fixup);
diff --git a/arch/mips/pci/ops-ddb5074.c b/arch/mips/pci/ops-ddb5074.c
deleted file mode 100644
index 89f97bef4fc4..000000000000
--- a/arch/mips/pci/ops-ddb5074.c
+++ /dev/null
@@ -1,271 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * arch/mips/ddb5xxx/ddb5476/pci_ops.c
6 * Define the pci_ops for DB5477.
7 *
8 * Much of the code is derived from the original DDB5074 port by
9 * Geert Uytterhoeven <geert@sonycom.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 */
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/types.h>
20
21#include <asm/addrspace.h>
22#include <asm/debug.h>
23
24#include <asm/ddb5xxx/ddb5xxx.h>
25
26/*
27 * config_swap structure records what set of pdar/pmr are used
28 * to access pci config space. It also provides a place hold the
29 * original values for future restoring.
30 */
31struct pci_config_swap {
32 u32 pdar;
33 u32 pmr;
34 u32 config_base;
35 u32 config_size;
36 u32 pdar_backup;
37 u32 pmr_backup;
38};
39
40/*
41 * On DDB5476, we have one set of swap registers
42 */
43struct pci_config_swap ext_pci_swap = {
44 DDB_PCIW0,
45 DDB_PCIINIT0,
46 DDB_PCI_CONFIG_BASE,
47 DDB_PCI_CONFIG_SIZE
48};
49
50static int pci_config_workaround = 1;
51
52/*
53 * access config space
54 */
55static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
56 u32 slot_num)
57{
58 u32 pci_addr = 0;
59 u32 pciinit_offset = 0;
60 u32 virt_addr = swap->config_base;
61 u32 option;
62
63 if (pci_config_workaround) {
64 if (slot_num == 5)
65 slot_num = 14;
66 } else {
67 if (slot_num == 5)
68 return DDB_BASE + DDB_PCI_BASE;
69 }
70
71 /* minimum pdar (window) size is 2MB */
72 db_assert(swap->config_size >= (2 << 20));
73
74 db_assert(slot_num < (1 << 5));
75 db_assert(bus < (1 << 8));
76
77 /* backup registers */
78 swap->pdar_backup = ddb_in32(swap->pdar);
79 swap->pmr_backup = ddb_in32(swap->pmr);
80
81 /* set the pdar (pci window) register */
82 ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
83 0, /* not on local memory bus */
84 0); /* not visible from PCI bus (N/A) */
85
86 /*
87 * calcuate the absolute pci config addr;
88 * according to the spec, we start scanning from adr:11 (0x800)
89 */
90 if (bus == 0) {
91 /* type 0 config */
92 pci_addr = 0x00040000 << slot_num;
93 } else {
94 /* type 1 config */
95 pci_addr = 0x00040000 << slot_num;
96 panic
97 ("ddb_access_config_base: we don't support type 1 config Yet");
98 }
99
100 /*
101 * if pci_addr is less than pci config window size, we set
102 * pciinit_offset to 0 and adjust the virt_address.
103 * Otherwise we will try to adjust pciinit_offset.
104 */
105 if (pci_addr < swap->config_size) {
106 virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
107 pciinit_offset = 0;
108 } else {
109 db_assert((pci_addr & (swap->config_size - 1)) == 0);
110 virt_addr = KSEG1ADDR(swap->config_base);
111 pciinit_offset = pci_addr;
112 }
113
114 /* set the pmr register */
115 option = DDB_PCI_ACCESS_32;
116 if (bus != 0)
117 option |= DDB_PCI_CFGTYPE1;
118 ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
119
120 return virt_addr;
121}
122
123static inline void ddb_close_config_base(struct pci_config_swap *swap)
124{
125 ddb_out32(swap->pdar, swap->pdar_backup);
126 ddb_out32(swap->pmr, swap->pmr_backup);
127}
128
129static int read_config_dword(struct pci_config_swap *swap,
130 struct pci_dev *dev, u32 where, u32 * val)
131{
132 u32 bus, slot_num, func_num;
133 u32 base;
134
135 db_assert((where & 3) == 0);
136 db_assert(where < (1 << 8));
137
138 /* check if the bus is top-level */
139 if (dev->bus->parent != NULL) {
140 bus = dev->bus->number;
141 db_assert(bus != 0);
142 } else {
143 bus = 0;
144 }
145
146 slot_num = PCI_SLOT(dev->devfn);
147 func_num = PCI_FUNC(dev->devfn);
148 base = ddb_access_config_base(swap, bus, slot_num);
149 *val = *(volatile u32 *) (base + (func_num << 8) + where);
150 ddb_close_config_base(swap);
151 return PCIBIOS_SUCCESSFUL;
152}
153
154static int read_config_word(struct pci_config_swap *swap,
155 struct pci_dev *dev, u32 where, u16 * val)
156{
157 int status;
158 u32 result;
159
160 db_assert((where & 1) == 0);
161
162 status = read_config_dword(swap, dev, where & ~3, &result);
163 if (where & 2)
164 result >>= 16;
165 *val = result & 0xffff;
166 return status;
167}
168
169static int read_config_byte(struct pci_config_swap *swap,
170 struct pci_dev *dev, u32 where, u8 * val)
171{
172 int status;
173 u32 result;
174
175 status = read_config_dword(swap, dev, where & ~3, &result);
176 if (where & 1)
177 result >>= 8;
178 if (where & 2)
179 result >>= 16;
180 *val = result & 0xff;
181 return status;
182}
183
184static int write_config_dword(struct pci_config_swap *swap,
185 struct pci_dev *dev, u32 where, u32 val)
186{
187 u32 bus, slot_num, func_num;
188 u32 base;
189
190 db_assert((where & 3) == 0);
191 db_assert(where < (1 << 8));
192
193 /* check if the bus is top-level */
194 if (dev->bus->parent != NULL) {
195 bus = dev->bus->number;
196 db_assert(bus != 0);
197 } else {
198 bus = 0;
199 }
200
201 slot_num = PCI_SLOT(dev->devfn);
202 func_num = PCI_FUNC(dev->devfn);
203 base = ddb_access_config_base(swap, bus, slot_num);
204 *(volatile u32 *) (base + (func_num << 8) + where) = val;
205 ddb_close_config_base(swap);
206 return PCIBIOS_SUCCESSFUL;
207}
208
209static int write_config_word(struct pci_config_swap *swap,
210 struct pci_dev *dev, u32 where, u16 val)
211{
212 int status, shift = 0;
213 u32 result;
214
215 db_assert((where & 1) == 0);
216
217 status = read_config_dword(swap, dev, where & ~3, &result);
218 if (status != PCIBIOS_SUCCESSFUL)
219 return status;
220
221 if (where & 2)
222 shift += 16;
223 result &= ~(0xffff << shift);
224 result |= val << shift;
225 return write_config_dword(swap, dev, where & ~3, result);
226}
227
228static int write_config_byte(struct pci_config_swap *swap,
229 struct pci_dev *dev, u32 where, u8 val)
230{
231 int status, shift = 0;
232 u32 result;
233
234 status = read_config_dword(swap, dev, where & ~3, &result);
235 if (status != PCIBIOS_SUCCESSFUL)
236 return status;
237
238 if (where & 2)
239 shift += 16;
240 if (where & 1)
241 shift += 8;
242 result &= ~(0xff << shift);
243 result |= val << shift;
244 return write_config_dword(swap, dev, where & ~3, result);
245}
246
247#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
248static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
249{ \
250 return rw##_config_##unitname(pciswap, \
251 dev, \
252 where, \
253 val); \
254}
255
256MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
257 MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
258 MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
259
260 MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
261 MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
262 MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
263
264struct pci_ops ddb5476_ext_pci_ops = {
265 extpci_read_config_byte,
266 extpci_read_config_word,
267 extpci_read_config_dword,
268 extpci_write_config_byte,
269 extpci_write_config_word,
270 extpci_write_config_dword
271};
diff --git a/arch/mips/pci/pci-ddb5074.c b/arch/mips/pci/pci-ddb5074.c
deleted file mode 100644
index b74158d9b4b1..000000000000
--- a/arch/mips/pci/pci-ddb5074.c
+++ /dev/null
@@ -1,79 +0,0 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/types.h>
4#include <linux/pci.h>
5
6#include <asm/debug.h>
7
8#include <asm/ddb5xxx/ddb5xxx.h>
9
10static struct resource extpci_io_resource = {
11 .start = 0x1000, /* leave some room for ISA bus */
12 .end = DDB_PCI_IO_SIZE - 1,
13 .name = "pci IO space",
14 .flags = IORESOURCE_IO
15};
16
17static struct resource extpci_mem_resource = {
18 .start = DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
19 .end = DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
20 .name = "pci memory space",
21 .flags = IORESOURCE_MEM
22};
23
24extern struct pci_ops ddb5476_ext_pci_ops;
25
26struct pci_controller ddb5476_controller = {
27 .pci_ops = &ddb5476_ext_pci_ops,
28 .io_resource = &extpci_io_resource,
29 .mem_resource = &extpci_mem_resource,
30};
31
32#define PCI_EXT_INTA 8
33#define PCI_EXT_INTB 9
34#define PCI_EXT_INTC 10
35#define PCI_EXT_INTD 11
36#define PCI_EXT_INTE 12
37
38#define MAX_SLOT_NUM 14
39
40static unsigned char irq_map[MAX_SLOT_NUM] = {
41 [ 0] = nile4_to_irq(PCI_EXT_INTE),
42 [ 1] = nile4_to_irq(PCI_EXT_INTA),
43 [ 2] = nile4_to_irq(PCI_EXT_INTA),
44 [ 3] = nile4_to_irq(PCI_EXT_INTB),
45 [ 4] = nile4_to_irq(PCI_EXT_INTC),
46 [ 5] = nile4_to_irq(NILE4_INT_UART),
47 [10] = nile4_to_irq(PCI_EXT_INTE),
48 [13] = nile4_to_irq(PCI_EXT_INTE),
49};
50
51int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
52{
53 return irq_map[slot];
54}
55
56/* Do platform specific device initialization at pci_enable_device() time */
57int pcibios_plat_dev_init(struct pci_dev *dev)
58{
59 return 0;
60}
61
62void __init ddb_pci_reset_bus(void)
63{
64 u32 temp;
65
66 /*
67 * I am not sure about the "official" procedure, the following
68 * steps work as far as I know:
69 * We first set PCI cold reset bit (bit 31) in PCICTRL-H.
70 * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
71 * The same is true for both PCI channels.
72 */
73 temp = ddb_in32(DDB_PCICTRL + 4);
74 temp |= 0x80000000;
75 ddb_out32(DDB_PCICTRL + 4, temp);
76 temp &= ~0xc0000000;
77 ddb_out32(DDB_PCICTRL + 4, temp);
78
79}
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