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authorDavid Daney <ddaney@caviumnetworks.com>2010-07-26 21:14:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2010-08-05 08:26:27 -0400
commit1aa2b2782a056b9bb0a19fae5a04624d8dcd8379 (patch)
treeb6e1197e9f83b1a155a9689e774741828780d84f /arch/mips/pci
parent0c2f4551df3880083e4733b5d928d2758b71162c (diff)
MIPS: Octeon: Support 256 MSI on PCIe
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1507/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/msi-octeon.c294
1 files changed, 177 insertions, 117 deletions
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 83ceb52d6e0e..7c756408b85d 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2005-2009 Cavium Networks 6 * Copyright (C) 2005-2009, 2010 Cavium Networks
7 */ 7 */
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9#include <linux/init.h> 9#include <linux/init.h>
@@ -22,7 +22,7 @@
22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is 22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
23 * in use. 23 * in use.
24 */ 24 */
25static uint64_t msi_free_irq_bitmask; 25static u64 msi_free_irq_bitmask[4];
26 26
27/* 27/*
28 * Each bit in msi_multiple_irq_bitmask tells that the device using 28 * Each bit in msi_multiple_irq_bitmask tells that the device using
@@ -30,7 +30,7 @@ static uint64_t msi_free_irq_bitmask;
30 * is used so we can disable all of the MSI interrupts when a device 30 * is used so we can disable all of the MSI interrupts when a device
31 * uses multiple. 31 * uses multiple.
32 */ 32 */
33static uint64_t msi_multiple_irq_bitmask; 33static u64 msi_multiple_irq_bitmask[4];
34 34
35/* 35/*
36 * This lock controls updates to msi_free_irq_bitmask and 36 * This lock controls updates to msi_free_irq_bitmask and
@@ -38,6 +38,11 @@ static uint64_t msi_multiple_irq_bitmask;
38 */ 38 */
39static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock); 39static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
40 40
41/*
42 * Number of MSI IRQs used. This variable is set up in
43 * the module init time.
44 */
45static int msi_irq_size;
41 46
42/** 47/**
43 * Called when a driver request MSI interrupts instead of the 48 * Called when a driver request MSI interrupts instead of the
@@ -54,12 +59,13 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
54int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 59int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
55{ 60{
56 struct msi_msg msg; 61 struct msi_msg msg;
57 uint16_t control; 62 u16 control;
58 int configured_private_bits; 63 int configured_private_bits;
59 int request_private_bits; 64 int request_private_bits;
60 int irq; 65 int irq = 0;
61 int irq_step; 66 int irq_step;
62 uint64_t search_mask; 67 u64 search_mask;
68 int index;
63 69
64 /* 70 /*
65 * Read the MSI config to figure out how many IRQs this device 71 * Read the MSI config to figure out how many IRQs this device
@@ -111,29 +117,31 @@ try_only_one:
111 * use. 117 * use.
112 */ 118 */
113 spin_lock(&msi_free_irq_bitmask_lock); 119 spin_lock(&msi_free_irq_bitmask_lock);
114 for (irq = 0; irq < 64; irq += irq_step) { 120 for (index = 0; index < msi_irq_size/64; index++) {
115 if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) { 121 for (irq = 0; irq < 64; irq += irq_step) {
116 msi_free_irq_bitmask |= search_mask << irq; 122 if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
117 msi_multiple_irq_bitmask |= (search_mask >> 1) << irq; 123 msi_free_irq_bitmask[index] |= search_mask << irq;
118 break; 124 msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
125 goto msi_irq_allocated;
126 }
119 } 127 }
120 } 128 }
129msi_irq_allocated:
121 spin_unlock(&msi_free_irq_bitmask_lock); 130 spin_unlock(&msi_free_irq_bitmask_lock);
122 131
123 /* Make sure the search for available interrupts didn't fail */ 132 /* Make sure the search for available interrupts didn't fail */
124 if (irq >= 64) { 133 if (irq >= 64) {
125 if (request_private_bits) { 134 if (request_private_bits) {
126 pr_err("arch_setup_msi_irq: Unable to find %d free " 135 pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
127 "interrupts, trying just one",
128 1 << request_private_bits); 136 1 << request_private_bits);
129 request_private_bits = 0; 137 request_private_bits = 0;
130 goto try_only_one; 138 goto try_only_one;
131 } else 139 } else
132 panic("arch_setup_msi_irq: Unable to find a free MSI " 140 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
133 "interrupt");
134 } 141 }
135 142
136 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */ 143 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
144 irq += index*64;
137 irq += OCTEON_IRQ_MSI_BIT0; 145 irq += OCTEON_IRQ_MSI_BIT0;
138 146
139 switch (octeon_dma_bar_type) { 147 switch (octeon_dma_bar_type) {
@@ -179,12 +187,18 @@ try_only_one:
179void arch_teardown_msi_irq(unsigned int irq) 187void arch_teardown_msi_irq(unsigned int irq)
180{ 188{
181 int number_irqs; 189 int number_irqs;
182 uint64_t bitmask; 190 u64 bitmask;
191 int index = 0;
192 int irq0;
183 193
184 if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_LAST)) 194 if ((irq < OCTEON_IRQ_MSI_BIT0)
195 || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
185 panic("arch_teardown_msi_irq: Attempted to teardown illegal " 196 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
186 "MSI interrupt (%d)", irq); 197 "MSI interrupt (%d)", irq);
198
187 irq -= OCTEON_IRQ_MSI_BIT0; 199 irq -= OCTEON_IRQ_MSI_BIT0;
200 index = irq / 64;
201 irq0 = irq % 64;
188 202
189 /* 203 /*
190 * Count the number of IRQs we need to free by looking at the 204 * Count the number of IRQs we need to free by looking at the
@@ -192,151 +206,197 @@ void arch_teardown_msi_irq(unsigned int irq)
192 * IRQ is also owned by this device. 206 * IRQ is also owned by this device.
193 */ 207 */
194 number_irqs = 0; 208 number_irqs = 0;
195 while ((irq+number_irqs < 64) && 209 while ((irq0 + number_irqs < 64) &&
196 (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs)))) 210 (msi_multiple_irq_bitmask[index]
211 & (1ull << (irq0 + number_irqs))))
197 number_irqs++; 212 number_irqs++;
198 number_irqs++; 213 number_irqs++;
199 /* Mask with one bit for each IRQ */ 214 /* Mask with one bit for each IRQ */
200 bitmask = (1 << number_irqs) - 1; 215 bitmask = (1 << number_irqs) - 1;
201 /* Shift the mask to the correct bit location */ 216 /* Shift the mask to the correct bit location */
202 bitmask <<= irq; 217 bitmask <<= irq0;
203 if ((msi_free_irq_bitmask & bitmask) != bitmask) 218 if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
204 panic("arch_teardown_msi_irq: Attempted to teardown MSI " 219 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
205 "interrupt (%d) not in use", irq); 220 "interrupt (%d) not in use", irq);
206 221
207 /* Checks are done, update the in use bitmask */ 222 /* Checks are done, update the in use bitmask */
208 spin_lock(&msi_free_irq_bitmask_lock); 223 spin_lock(&msi_free_irq_bitmask_lock);
209 msi_free_irq_bitmask &= ~bitmask; 224 msi_free_irq_bitmask[index] &= ~bitmask;
210 msi_multiple_irq_bitmask &= ~bitmask; 225 msi_multiple_irq_bitmask[index] &= ~bitmask;
211 spin_unlock(&msi_free_irq_bitmask_lock); 226 spin_unlock(&msi_free_irq_bitmask_lock);
212} 227}
213 228
229static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
214 230
215/* 231static u64 msi_rcv_reg[4];
216 * Called by the interrupt handling code when an MSI interrupt 232static u64 mis_ena_reg[4];
217 * occurs. 233
218 */ 234static void octeon_irq_msi_enable_pcie(unsigned int irq)
219static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
220{ 235{
221 uint64_t msi_bits; 236 u64 en;
222 int irq; 237 unsigned long flags;
238 int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
239 int irq_index = msi_number >> 6;
240 int irq_bit = msi_number & 0x3f;
241
242 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
243 en = cvmx_read_csr(mis_ena_reg[irq_index]);
244 en |= 1ull << irq_bit;
245 cvmx_write_csr(mis_ena_reg[irq_index], en);
246 cvmx_read_csr(mis_ena_reg[irq_index]);
247 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
248}
223 249
224 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) 250static void octeon_irq_msi_disable_pcie(unsigned int irq)
225 msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0); 251{
226 else 252 u64 en;
227 msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV); 253 unsigned long flags;
228 irq = fls64(msi_bits); 254 int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
229 if (irq) { 255 int irq_index = msi_number >> 6;
230 irq += OCTEON_IRQ_MSI_BIT0 - 1; 256 int irq_bit = msi_number & 0x3f;
231 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 257
232 /* These chips have PCIe */ 258 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
233 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, 259 en = cvmx_read_csr(mis_ena_reg[irq_index]);
234 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); 260 en &= ~(1ull << irq_bit);
235 } else { 261 cvmx_write_csr(mis_ena_reg[irq_index], en);
236 /* These chips have PCI */ 262 cvmx_read_csr(mis_ena_reg[irq_index]);
237 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, 263 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
238 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
239 }
240 if (irq_desc[irq].action) {
241 do_IRQ(irq);
242 return IRQ_HANDLED;
243 } else {
244 pr_err("Spurious MSI interrupt %d\n", irq);
245 }
246 }
247 return IRQ_NONE;
248} 264}
249 265
250static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); 266static struct irq_chip octeon_irq_chip_msi_pcie = {
267 .name = "MSI",
268 .enable = octeon_irq_msi_enable_pcie,
269 .disable = octeon_irq_msi_disable_pcie,
270};
251 271
252static void octeon_irq_msi_enable(unsigned int irq) 272static void octeon_irq_msi_enable_pci(unsigned int irq)
253{ 273{
254 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { 274 /*
255 /* 275 * Octeon PCI doesn't have the ability to mask/unmask MSI
256 * Octeon PCI doesn't have the ability to mask/unmask 276 * interrupts individually. Instead of masking/unmasking them
257 * MSI interrupts individually. Instead of 277 * in groups of 16, we simple assume MSI devices are well
258 * masking/unmasking them in groups of 16, we simple 278 * behaved. MSI interrupts are always enable and the ACK is
259 * assume MSI devices are well behaved. MSI 279 * assumed to be enough
260 * interrupts are always enable and the ACK is assumed 280 */
261 * to be enough.
262 */
263 } else {
264 /* These chips have PCIe. Note that we only support
265 * the first 64 MSI interrupts. Unfortunately all the
266 * MSI enables are in the same register. We use
267 * MSI0's lock to control access to them all.
268 */
269 uint64_t en;
270 unsigned long flags;
271 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
272 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
273 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
274 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
275 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
276 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
277 }
278} 281}
279 282
280static void octeon_irq_msi_disable(unsigned int irq) 283static void octeon_irq_msi_disable_pci(unsigned int irq)
281{ 284{
282 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { 285 /* See comment in enable */
283 /* See comment in enable */
284 } else {
285 /*
286 * These chips have PCIe. Note that we only support
287 * the first 64 MSI interrupts. Unfortunately all the
288 * MSI enables are in the same register. We use
289 * MSI0's lock to control access to them all.
290 */
291 uint64_t en;
292 unsigned long flags;
293 raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
294 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
295 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
296 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
297 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
298 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
299 }
300} 286}
301 287
302static struct irq_chip octeon_irq_chip_msi = { 288static struct irq_chip octeon_irq_chip_msi_pci = {
303 .name = "MSI", 289 .name = "MSI",
304 .enable = octeon_irq_msi_enable, 290 .enable = octeon_irq_msi_enable_pci,
305 .disable = octeon_irq_msi_disable, 291 .disable = octeon_irq_msi_disable_pci,
306}; 292};
307 293
308/* 294/*
309 * Initializes the MSI interrupt handling code 295 * Called by the interrupt handling code when an MSI interrupt
296 * occurs.
310 */ 297 */
311static int __init octeon_msi_initialize(void) 298static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
312{ 299{
313 int irq; 300 int irq;
301 int bit;
314 302
315 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++) { 303 bit = fls64(msi_bits);
316 set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, handle_simple_irq); 304 if (bit) {
305 bit--;
306 /* Acknowledge it first. */
307 cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
308
309 irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
310 do_IRQ(irq);
311 return IRQ_HANDLED;
317 } 312 }
313 return IRQ_NONE;
314}
315
316#define OCTEON_MSI_INT_HANDLER_X(x) \
317static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
318{ \
319 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
320 return __octeon_msi_do_interrupt((x), msi_bits); \
321}
322
323/*
324 * Create octeon_msi_interrupt{0-3} function body
325 */
326OCTEON_MSI_INT_HANDLER_X(0);
327OCTEON_MSI_INT_HANDLER_X(1);
328OCTEON_MSI_INT_HANDLER_X(2);
329OCTEON_MSI_INT_HANDLER_X(3);
330
331/*
332 * Initializes the MSI interrupt handling code
333 */
334int __init octeon_msi_initialize(void)
335{
336 int irq;
337 struct irq_chip *msi;
338
339 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
340 msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
341 msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
342 msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
343 msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
344 mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
345 mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
346 mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
347 mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
348 msi = &octeon_irq_chip_msi_pcie;
349 } else {
350 msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
351#define INVALID_GENERATE_ADE 0x8700000000000000ULL;
352 msi_rcv_reg[1] = INVALID_GENERATE_ADE;
353 msi_rcv_reg[2] = INVALID_GENERATE_ADE;
354 msi_rcv_reg[3] = INVALID_GENERATE_ADE;
355 mis_ena_reg[0] = INVALID_GENERATE_ADE;
356 mis_ena_reg[1] = INVALID_GENERATE_ADE;
357 mis_ena_reg[2] = INVALID_GENERATE_ADE;
358 mis_ena_reg[3] = INVALID_GENERATE_ADE;
359 msi = &octeon_irq_chip_msi_pci;
360 }
361
362 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
363 set_irq_chip_and_handler(irq, msi, handle_simple_irq);
318 364
319 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) { 365 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
320 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, 366 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
321 0, "MSI[0:63]", octeon_msi_interrupt)) 367 0, "MSI[0:63]", octeon_msi_interrupt0))
322 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 368 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
369
370 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
371 0, "MSI[64:127]", octeon_msi_interrupt1))
372 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
373
374 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
375 0, "MSI[127:191]", octeon_msi_interrupt2))
376 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
377
378 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
379 0, "MSI[192:255]", octeon_msi_interrupt3))
380 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
381
382 msi_irq_size = 256;
323 } else if (octeon_is_pci_host()) { 383 } else if (octeon_is_pci_host()) {
324 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt, 384 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
325 0, "MSI[0:15]", octeon_msi_interrupt)) 385 0, "MSI[0:15]", octeon_msi_interrupt0))
326 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed"); 386 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
327 387
328 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt, 388 if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
329 0, "MSI[16:31]", octeon_msi_interrupt)) 389 0, "MSI[16:31]", octeon_msi_interrupt0))
330 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed"); 390 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
331 391
332 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt, 392 if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
333 0, "MSI[32:47]", octeon_msi_interrupt)) 393 0, "MSI[32:47]", octeon_msi_interrupt0))
334 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed"); 394 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
335 395
336 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt, 396 if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
337 0, "MSI[48:63]", octeon_msi_interrupt)) 397 0, "MSI[48:63]", octeon_msi_interrupt0))
338 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed"); 398 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
339 399 msi_irq_size = 64;
340 } 400 }
341 return 0; 401 return 0;
342} 402}