Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (141 commits)
  MIPS: Alchemy: defconfig updates
  MIPS: Alchemy: Fix Au1100 ethernet build failure
  MIPS: Alchemy: Repair db1500/bosporus builds
  MIPS: ARC: Cleanup unused definitions from sgialib.h
  MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses
  MIPS: Alchemy: use 36bit addresses for PCMCIA resources.
  MIPS: Cobalt: Fix theoretical port aliasing issue
  MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1)
  MIPS: Crazy spinlock speed test.
  MIPS: Optimize spinlocks.
  MIPS: Alchemy: devboard PM needs to save CPLD registers.
  MIPS: PowerTV: Eliminate duplicate opcode definition macros
  MIPS: Lemote 2F: Move printks out of port_access_lock.
  MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks.
  MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.
  MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks.
  MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock.
  MIPS: Loongson: Remove pointless sample_lock from oprofile code.
  MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.
  MIPS: i8259: Convert IRQ controller lock to raw spinlock.
  ...

7 files changed, 66 insertions, 12 deletions

diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dd..acacd1407c63 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,6 +51,67 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
+static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
+                                                       struct resource *res)
+{
+        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
+        unsigned long offset = hose->io_offset;
+        struct resource orig = *res;
+
+        if (!(res->flags & IORESOURCE_IO) ||
+            !(res->flags & IORESOURCE_PCI_FIXED))
+                return;
+
+        res->start -= offset;
+        res->end -= offset;
+        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
+                   &orig, res);
+}
+
+static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
+{
+        u32 class;
+        u8 progif;
+
+        /*
+         * If the IDE controller is in legacy mode, pci_setup_device() fills in
+         * the resources with the legacy addresses that normally appear on the
+         * PCI bus, just as if we had read them from a BAR.
+         *
+         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
+         * will never appear on the PCI bus because it converts memory accesses
+         * in the PCI I/O region (which is never at address zero) into I/O port
+         * accesses with no address translation.
+         *
+         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
+         * to physical address 0x100001f0 will become a PCI access to I/O port
+         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
+         * but the VT82C586 IDE controller does respond at 0x100001f0 because
+         * it only decodes the low 24 bits of the address.
+         *
+         * When this quirk runs, the pci_dev resources should contain bus
+         * addresses, not Linux I/O port numbers, so convert legacy addresses
+         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
+         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
+         */
+        class = dev->class >> 8;
+        if (class != PCI_CLASS_STORAGE_IDE)
+                return;
+
+        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
+        if ((progif & 1) == 0) {
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
+        }
+        if ((progif & 4) == 0) {
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
+        }
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
+          cobalt_legacy_ide_fixup);
+
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index caf2edeb02f0..4b9768d5d729 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -131,7 +131,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
 
         /* Serial short detect enable */
         _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
-        _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
+        _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 3), lo);
 
         /* setting the USB2.0 micro frame length */
         pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index aa5d3da27212..2bb4057bf6c7 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -1,13 +1,11 @@
 /*
- * fuloong2e specific PCI support.
- *
  * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
  *      All rights reserved.
  *      Authors: Carsten Langgaard <carstenl@mips.com>
  *               Maciej W. Rozycki <macro@mips.com>
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 32548b5d68d6..04b31478a6d7 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -206,7 +206,7 @@ static void pci_proc_init(void)
 }
 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
 
-DEFINE_SPINLOCK(bpci_lock);
+static DEFINE_SPINLOCK(bpci_lock);
 
 /*****************************************************************************
  *
diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
index bea9b6cdfdbf..455f8e50a007 100644
--- a/arch/mips/pci/pci-bcm47xx.c
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -57,4 +57,3 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         dev->irq = res;
         return 0;
 }
-
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 9cb0c807f564..d248b707eff3 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -209,16 +209,14 @@ const char *octeon_get_pci_interrupts(void)
         case CVMX_BOARD_TYPE_NAO38:
                 /* This is really the NAC38 */
                 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
-        case CVMX_BOARD_TYPE_THUNDER:
-                return "";
-        case CVMX_BOARD_TYPE_EBH3000:
-                return "";
         case CVMX_BOARD_TYPE_EBH3100:
         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
                 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
         case CVMX_BOARD_TYPE_BBGW_REF:
                 return "AABCD";
+        case CVMX_BOARD_TYPE_THUNDER:
+        case CVMX_BOARD_TYPE_EBH3000:
         default:
                 return "";
         }
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index f87f5e188fa6..38bc28005b4a 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -251,8 +251,6 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
                 if (!dev->resource[i].start)
                         continue;
-                if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
-                        continue;
                 if (dev->resource[i].flags & IORESOURCE_IO)
                         offset = hose->io_offset;
                 else if (dev->resource[i].flags & IORESOURCE_MEM)