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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2008-04-30 15:23:27 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-05-12 11:46:52 -0400
commita9633279cf13de15b7002b71a507baf89d0619ca (patch)
tree39afe61bc9a862cbde6cdfc8cd2d10411c8fcfeb /arch/mips/pci
parentc1dcb14ec2ae3c594ce1c2db953004083f2bd4a0 (diff)
[MIPS] Alchemy PCI code style cleanup
Fix 15 errors and 4 warnings given by checkpatch.pl: - space between the asterisk and variable name; - space after opening and before closing parentheses; - leading spaces instead of tabs; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - line over 80 characters. In addition to these changes, also do the following: - combine the nested 'if' statements into one when possible; - remove needless parentheses; - add missing and remove excess spaces between operator and its operands; - fix printk() format specifiers mismatching the argument types; - put the function's result type and name/parameters on the same line; - insert missing and remove excess new lines; - properly indent multi-line expressions; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line; - fix typos, capitalize acronyms, etc. in the comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/fixup-au1000.c7
-rw-r--r--arch/mips/pci/ops-au1000.c115
2 files changed, 56 insertions, 66 deletions
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
index 00c36c9dbe0e..e2ddfc49237c 100644
--- a/arch/mips/pci/fixup-au1000.c
+++ b/arch/mips/pci/fixup-au1000.c
@@ -1,10 +1,9 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Board specific pci fixups. 3 * Board specific PCI fixups.
4 * 4 *
5 * Copyright 2001-2003 MontaVista Software Inc. 5 * Copyright 2001-2003, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 * ppopov@mvista.com or source@mvista.com
8 * 7 *
9 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 1314bd58f036..9a57c5ab91dd 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -1,10 +1,9 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Alchemy/AMD Au1x00 PCI support. 3 * Alchemy/AMD Au1xx0 PCI support.
4 * 4 *
5 * Copyright 2001-2003, 2007 MontaVista Software Inc. 5 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. 6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 * ppopov@mvista.com or source@mvista.com
8 * 7 *
9 * Support for all devices (greater than 16) added by David Gathright. 8 * Support for all devices (greater than 16) added by David Gathright.
10 * 9 *
@@ -28,6 +27,7 @@
28 * with this program; if not, write to the Free Software Foundation, Inc., 27 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 */ 29 */
30
31#include <linux/types.h> 31#include <linux/types.h>
32#include <linux/pci.h> 32#include <linux/pci.h>
33#include <linux/kernel.h> 33#include <linux/kernel.h>
@@ -36,9 +36,9 @@
36 36
37#include <asm/mach-au1x00/au1000.h> 37#include <asm/mach-au1x00/au1000.h>
38 38
39#undef DEBUG 39#undef DEBUG
40#ifdef DEBUG 40#ifdef DEBUG
41#define DBG(x...) printk(x) 41#define DBG(x...) printk(KERN_DEBUG x)
42#else 42#else
43#define DBG(x...) 43#define DBG(x...)
44#endif 44#endif
@@ -46,7 +46,6 @@
46#define PCI_ACCESS_READ 0 46#define PCI_ACCESS_READ 0
47#define PCI_ACCESS_WRITE 1 47#define PCI_ACCESS_WRITE 1
48 48
49
50int (*board_pci_idsel)(unsigned int devsel, int assert); 49int (*board_pci_idsel)(unsigned int devsel, int assert);
51 50
52void mod_wired_entry(int entry, unsigned long entrylo0, 51void mod_wired_entry(int entry, unsigned long entrylo0,
@@ -92,10 +91,9 @@ void __init au1x_pci_cfg_init(void)
92} 91}
93 92
94static int config_access(unsigned char access_type, struct pci_bus *bus, 93static int config_access(unsigned char access_type, struct pci_bus *bus,
95 unsigned int dev_fn, unsigned char where, 94 unsigned int dev_fn, unsigned char where, u32 *data)
96 u32 * data)
97{ 95{
98#if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 ) 96#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
99 unsigned int device = PCI_SLOT(dev_fn); 97 unsigned int device = PCI_SLOT(dev_fn);
100 unsigned int function = PCI_FUNC(dev_fn); 98 unsigned int function = PCI_FUNC(dev_fn);
101 unsigned long offset, status; 99 unsigned long offset, status;
@@ -114,38 +112,36 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
114 Au1500_PCI_STATCMD); 112 Au1500_PCI_STATCMD);
115 au_sync_udelay(1); 113 au_sync_udelay(1);
116 114
117 /* Allow board vendors to implement their own off-chip idsel. 115 /*
116 * Allow board vendors to implement their own off-chip IDSEL.
118 * If it doesn't succeed, may as well bail out at this point. 117 * If it doesn't succeed, may as well bail out at this point.
119 */ 118 */
120 if (board_pci_idsel) { 119 if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {
121 if (board_pci_idsel(device, 1) == 0) { 120 *data = 0xffffffff;
122 *data = 0xffffffff; 121 local_irq_restore(flags);
123 local_irq_restore(flags); 122 return -1;
124 return -1;
125 }
126 } 123 }
127 124
128 /* setup the config window */ 125 /* Setup the config window */
129 if (bus->number == 0) { 126 if (bus->number == 0)
130 cfg_base = ((1<<device)<<11); 127 cfg_base = (1 << device) << 11;
131 } else { 128 else
132 cfg_base = 0x80000000 | (bus->number<<16) | (device<<11); 129 cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
133 }
134 130
135 /* setup the lower bits of the 36 bit address */ 131 /* Setup the lower bits of the 36-bit address */
136 offset = (function << 8) | (where & ~0x3); 132 offset = (function << 8) | (where & ~0x3);
137 /* pick up any address that falls below the page mask */ 133 /* Pick up any address that falls below the page mask */
138 offset |= cfg_base & ~PAGE_MASK; 134 offset |= cfg_base & ~PAGE_MASK;
139 135
140 /* page boundary */ 136 /* Page boundary */
141 cfg_base = cfg_base & PAGE_MASK; 137 cfg_base = cfg_base & PAGE_MASK;
142 138
143 /* 139 /*
144 * To improve performance, if the current device is the same as 140 * To improve performance, if the current device is the same as
145 * the last device accessed, we don't touch the TLB. 141 * the last device accessed, we don't touch the TLB.
146 */ 142 */
147 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; 143 entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
148 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; 144 entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
149 if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { 145 if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
150 mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, 146 mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
151 (unsigned long)pci_cfg_vm->addr, PM_4K); 147 (unsigned long)pci_cfg_vm->addr, PM_4K);
@@ -153,38 +149,37 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
153 last_entryLo1 = entryLo1; 149 last_entryLo1 = entryLo1;
154 } 150 }
155 151
156 if (access_type == PCI_ACCESS_WRITE) { 152 if (access_type == PCI_ACCESS_WRITE)
157 au_writel(*data, (int)(pci_cfg_vm->addr + offset)); 153 au_writel(*data, (int)(pci_cfg_vm->addr + offset));
158 } else { 154 else
159 *data = au_readl((int)(pci_cfg_vm->addr + offset)); 155 *data = au_readl((int)(pci_cfg_vm->addr + offset));
160 } 156
161 au_sync_udelay(2); 157 au_sync_udelay(2);
162 158
163 DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n", 159 DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",
164 access_type, bus->number, device, where, *data, offset); 160 access_type, bus->number, device, where, *data, offset);
165 161
166 /* check master abort */ 162 /* Check master abort */
167 status = au_readl(Au1500_PCI_STATCMD); 163 status = au_readl(Au1500_PCI_STATCMD);
168 164
169 if (status & (1<<29)) { 165 if (status & (1 << 29)) {
170 *data = 0xffffffff; 166 *data = 0xffffffff;
171 error = -1; 167 error = -1;
172 DBG("Au1x Master Abort\n"); 168 DBG("Au1x Master Abort\n");
173 } else if ((status >> 28) & 0xf) { 169 } else if ((status >> 28) & 0xf) {
174 DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf)); 170 DBG("PCI ERR detected: device %u, status %lx\n",
171 device, (status >> 28) & 0xf);
175 172
176 /* clear errors */ 173 /* Clear errors */
177 au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); 174 au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
178 175
179 *data = 0xffffffff; 176 *data = 0xffffffff;
180 error = -1; 177 error = -1;
181 } 178 }
182 179
183 /* Take away the idsel. 180 /* Take away the IDSEL. */
184 */ 181 if (board_pci_idsel)
185 if (board_pci_idsel) {
186 (void)board_pci_idsel(device, 0); 182 (void)board_pci_idsel(device, 0);
187 }
188 183
189 local_irq_restore(flags); 184 local_irq_restore(flags);
190 return error; 185 return error;
@@ -192,7 +187,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
192} 187}
193 188
194static int read_config_byte(struct pci_bus *bus, unsigned int devfn, 189static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
195 int where, u8 * val) 190 int where, u8 *val)
196{ 191{
197 u32 data; 192 u32 data;
198 int ret; 193 int ret;
@@ -206,9 +201,8 @@ static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
206 return ret; 201 return ret;
207} 202}
208 203
209
210static int read_config_word(struct pci_bus *bus, unsigned int devfn, 204static int read_config_word(struct pci_bus *bus, unsigned int devfn,
211 int where, u16 * val) 205 int where, u16 *val)
212{ 206{
213 u32 data; 207 u32 data;
214 int ret; 208 int ret;
@@ -221,7 +215,7 @@ static int read_config_word(struct pci_bus *bus, unsigned int devfn,
221} 215}
222 216
223static int read_config_dword(struct pci_bus *bus, unsigned int devfn, 217static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
224 int where, u32 * val) 218 int where, u32 *val)
225{ 219{
226 int ret; 220 int ret;
227 221
@@ -229,9 +223,8 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
229 return ret; 223 return ret;
230} 224}
231 225
232static int 226static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
233write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, 227 int where, u8 val)
234 u8 val)
235{ 228{
236 u32 data = 0; 229 u32 data = 0;
237 230
@@ -239,7 +232,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
239 return -1; 232 return -1;
240 233
241 data = (data & ~(0xff << ((where & 3) << 3))) | 234 data = (data & ~(0xff << ((where & 3) << 3))) |
242 (val << ((where & 3) << 3)); 235 (val << ((where & 3) << 3));
243 236
244 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) 237 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
245 return -1; 238 return -1;
@@ -247,9 +240,8 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
247 return PCIBIOS_SUCCESSFUL; 240 return PCIBIOS_SUCCESSFUL;
248} 241}
249 242
250static int 243static int write_config_word(struct pci_bus *bus, unsigned int devfn,
251write_config_word(struct pci_bus *bus, unsigned int devfn, int where, 244 int where, u16 val)
252 u16 val)
253{ 245{
254 u32 data = 0; 246 u32 data = 0;
255 247
@@ -257,18 +249,16 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
257 return -1; 249 return -1;
258 250
259 data = (data & ~(0xffff << ((where & 3) << 3))) | 251 data = (data & ~(0xffff << ((where & 3) << 3))) |
260 (val << ((where & 3) << 3)); 252 (val << ((where & 3) << 3));
261 253
262 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) 254 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 return -1; 255 return -1;
264 256
265
266 return PCIBIOS_SUCCESSFUL; 257 return PCIBIOS_SUCCESSFUL;
267} 258}
268 259
269static int 260static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
270write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, 261 int where, u32 val)
271 u32 val)
272{ 262{
273 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) 263 if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
274 return -1; 264 return -1;
@@ -277,18 +267,20 @@ write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
277} 267}
278 268
279static int config_read(struct pci_bus *bus, unsigned int devfn, 269static int config_read(struct pci_bus *bus, unsigned int devfn,
280 int where, int size, u32 * val) 270 int where, int size, u32 *val)
281{ 271{
282 switch (size) { 272 switch (size) {
283 case 1: { 273 case 1: {
284 u8 _val; 274 u8 _val;
285 int rc = read_config_byte(bus, devfn, where, &_val); 275 int rc = read_config_byte(bus, devfn, where, &_val);
276
286 *val = _val; 277 *val = _val;
287 return rc; 278 return rc;
288 } 279 }
289 case 2: { 280 case 2: {
290 u16 _val; 281 u16 _val;
291 int rc = read_config_word(bus, devfn, where, &_val); 282 int rc = read_config_word(bus, devfn, where, &_val);
283
292 *val = _val; 284 *val = _val;
293 return rc; 285 return rc;
294 } 286 }
@@ -310,7 +302,6 @@ static int config_write(struct pci_bus *bus, unsigned int devfn,
310 } 302 }
311} 303}
312 304
313
314struct pci_ops au1x_pci_ops = { 305struct pci_ops au1x_pci_ops = {
315 config_read, 306 config_read,
316 config_write 307 config_write