Merge branch 'linux-2.6'

4 files changed, 37 insertions, 29 deletions

diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index f7df1142912b..9553b14002dd 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -177,7 +177,7 @@ static char irq_tab_raq2[] __initdata = {
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
-        if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
+        if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
                 return irq_tab_qube1[slot];
 
         if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 6b29904acf45..1314bd58f036 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -1,8 +1,8 @@
 /*
  * BRIEF MODULE DESCRIPTION
- *      Alchemy/AMD Au1x00 pci support.
+ *      Alchemy/AMD Au1x00 PCI support.
  *
- * Copyright 2001,2002,2003 MontaVista Software Inc.
+ * Copyright 2001-2003, 2007 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *              ppopov@mvista.com or source@mvista.com
  *
@@ -69,10 +69,27 @@ void mod_wired_entry(int entry, unsigned long entrylo0,
         write_c0_pagemask(old_pagemask);
 }
 
-struct vm_struct *pci_cfg_vm;
+static struct vm_struct *pci_cfg_vm;
 static int pci_cfg_wired_entry;
-static int first_cfg = 1;
-unsigned long last_entryLo0, last_entryLo1;
+static unsigned long last_entryLo0, last_entryLo1;
+
+/*
+ * We can't ioremap the entire pci config space because it's too large.
+ * Nor can we call ioremap dynamically because some device drivers use
+ * the PCI config routines from within interrupt handlers and that
+ * becomes a problem in get_vm_area().  We use one wired TLB to handle
+ * all config accesses for all busses.
+ */
+void __init au1x_pci_cfg_init(void)
+{
+        /* Reserve a wired entry for PCI config accesses */
+        pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
+        if (!pci_cfg_vm)
+                panic(KERN_ERR "PCI unable to get vm area\n");
+        pci_cfg_wired_entry = read_c0_wired();
+        add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
+        last_entryLo0 = last_entryLo1 = 0xffffffff;
+}
 
 static int config_access(unsigned char access_type, struct pci_bus *bus,
                          unsigned int dev_fn, unsigned char where,
@@ -97,27 +114,6 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
                         Au1500_PCI_STATCMD);
         au_sync_udelay(1);
 
-        /*
-         * We can't ioremap the entire pci config space because it's
-         * too large. Nor can we call ioremap dynamically because some
-         * device drivers use the pci config routines from within
-         * interrupt handlers and that becomes a problem in get_vm_area().
-         * We use one wired tlb to handle all config accesses for all
-         * busses. To improve performance, if the current device
-         * is the same as the last device accessed, we don't touch the
-         * tlb.
-         */
-        if (first_cfg) {
-                /* reserve a wired entry for pci config accesses */
-                first_cfg = 0;
-                pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
-                if (!pci_cfg_vm)
-                        panic(KERN_ERR "PCI unable to get vm area\n");
-                pci_cfg_wired_entry = read_c0_wired();
-                add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
-                last_entryLo0  = last_entryLo1 = 0xffffffff;
-        }
-
         /* Allow board vendors to implement their own off-chip idsel.
          * If it doesn't succeed, may as well bail out at this point.
          */
@@ -144,9 +140,12 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
         /* page boundary */
         cfg_base = cfg_base & PAGE_MASK;
 
+        /*
+         * To improve performance, if the current device is the same as
+         * the last device accessed, we don't touch the TLB.
+         */
         entryLo0 = (6 << 26)  | (cfg_base >> 6) | (2 << 3) | 7;
         entryLo1 = (6 << 26)  | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
-
         if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
                 mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
                                 (unsigned long)pci_cfg_vm->addr, PM_4K);
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index fe5451449304..e95881897ec9 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -42,6 +42,10 @@ static int
 mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                      int reg, int size, u32 *val)
 {
+        u32 control = mace->pci.control;
+
+        /* disable master aborts interrupts during config read */
+        mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
         mace->pci.config_addr = mkaddr(bus, devfn, reg);
         switch (size) {
         case 1:
@@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
                 *val = mace->pci.config_data.l;
                 break;
         }
+        /* ack possible master abort */
+        mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
+        mace->pci.control = control;
 
         DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
 
diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 618ea7dbc474..532b561b4442 100644
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -119,6 +119,7 @@ static struct pci_controller mace_pci_controller = {
         .iommu          = 0,
         .mem_offset     = MACE_PCI_MEM_OFFSET,
         .io_offset      = 0,
+        .io_map_base    = CKSEG1ADDR(MACEPCI_LOW_IO),
 };
 
 static int __init mace_init(void)
@@ -135,7 +136,8 @@ static int __init mace_init(void)
         BUG_ON(request_irq(MACE_PCI_BRIDGE_IRQ, macepci_error, 0,
                            "MACE PCI error", NULL));
 
-        iomem_resource = mace_pci_mem_resource;
+        /* extend memory resources */
+        iomem_resource.end = mace_pci_mem_resource.end;
         ioport_resource = mace_pci_io_resource;
 
         register_pci_controller(&mace_pci_controller);