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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-03-14 08:51:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-04-27 11:20:23 -0400
commit252161eccd1a44f32a506d0fedb424d4ff84e4dc (patch)
tree39c4c46d69b653b20047a0af7175f477ce54913e /arch/mips/pci
parent2a9effc67804102d6d5182eb0116520588ae2256 (diff)
[MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines
This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines. GT64111 PCI is almost the same as GT64120's PCI_0. This patch don't change GT64120 PCI routines. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/ops-gt64111.c100
-rw-r--r--arch/mips/pci/ops-gt64xxx_pci0.c (renamed from arch/mips/pci/ops-gt64120.c)30
-rw-r--r--arch/mips/pci/pci-lasat.c4
-rw-r--r--arch/mips/pci/pci-ocelot.c2
5 files changed, 19 insertions, 120 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index bf85995ca042..df487c063b1d 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -8,8 +8,7 @@ obj-y += pci.o pci-dac.o
8# PCI bus host bridge specific code 8# PCI bus host bridge specific code
9# 9#
10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
11obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o 11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
12obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
13obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o 12obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o
14obj-$(CONFIG_MIPS_MSC) += ops-msc.o 13obj-$(CONFIG_MIPS_MSC) += ops-msc.o
15obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o 14obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
diff --git a/arch/mips/pci/ops-gt64111.c b/arch/mips/pci/ops-gt64111.c
deleted file mode 100644
index ecd3991bd0e4..000000000000
--- a/arch/mips/pci/ops-gt64111.c
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle
7 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
8 */
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13
14#include <asm/pci.h>
15#include <asm/io.h>
16#include <asm/gt64120.h>
17
18#include <asm/mach-cobalt/cobalt.h>
19
20/*
21 * Device 31 on the GT64111 is used to generate PCI special
22 * cycles, so we shouldn't expected to find a device there ...
23 */
24static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn)
25{
26 if (bus->number == 0 && PCI_SLOT(devfn) < 31)
27 return 0;
28
29 return -1;
30}
31
32static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
33 int where, int size, u32 * val)
34{
35 if (pci_range_ck(bus, devfn))
36 return PCIBIOS_DEVICE_NOT_FOUND;
37
38 switch (size) {
39 case 4:
40 PCI_CFG_SET(devfn, where);
41 *val = GT_READ(GT_PCI0_CFGDATA_OFS);
42 return PCIBIOS_SUCCESSFUL;
43
44 case 2:
45 PCI_CFG_SET(devfn, (where & ~0x3));
46 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
47 >> ((where & 3) * 8);
48 return PCIBIOS_SUCCESSFUL;
49
50 case 1:
51 PCI_CFG_SET(devfn, (where & ~0x3));
52 *val = GT_READ(GT_PCI0_CFGDATA_OFS)
53 >> ((where & 3) * 8);
54 return PCIBIOS_SUCCESSFUL;
55 }
56
57 return PCIBIOS_BAD_REGISTER_NUMBER;
58}
59
60static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
61 int where, int size, u32 val)
62{
63 u32 tmp;
64
65 if (pci_range_ck(bus, devfn))
66 return PCIBIOS_DEVICE_NOT_FOUND;
67
68 switch (size) {
69 case 4:
70 PCI_CFG_SET(devfn, where);
71 GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
72
73 return PCIBIOS_SUCCESSFUL;
74
75 case 2:
76 PCI_CFG_SET(devfn, (where & ~0x3));
77 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
78 tmp &= ~(0xffff << ((where & 0x3) * 8));
79 tmp |= (val << ((where & 0x3) * 8));
80 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
81
82 return PCIBIOS_SUCCESSFUL;
83
84 case 1:
85 PCI_CFG_SET(devfn, (where & ~0x3));
86 tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
87 tmp &= ~(0xff << ((where & 0x3) * 8));
88 tmp |= (val << ((where & 0x3) * 8));
89 GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
90
91 return PCIBIOS_SUCCESSFUL;
92 }
93
94 return PCIBIOS_BAD_REGISTER_NUMBER;
95}
96
97struct pci_ops gt64111_pci_ops = {
98 .read = gt64111_pci_read_config,
99 .write = gt64111_pci_write_config,
100};
diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64xxx_pci0.c
index 6335844d607a..3d896c5f413f 100644
--- a/arch/mips/pci/ops-gt64120.c
+++ b/arch/mips/pci/ops-gt64xxx_pci0.c
@@ -39,8 +39,8 @@
39#define PCI_CFG_TYPE1_DEV_SHF 11 39#define PCI_CFG_TYPE1_DEV_SHF 11
40#define PCI_CFG_TYPE1_BUS_SHF 16 40#define PCI_CFG_TYPE1_BUS_SHF 16
41 41
42static int gt64120_pcibios_config_access(unsigned char access_type, 42static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 43 struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
44{ 44{
45 unsigned char busnum = bus->number; 45 unsigned char busnum = bus->number;
46 u32 intr; 46 u32 intr;
@@ -100,13 +100,13 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
100 * We can't address 8 and 16 bit words directly. Instead we have to 100 * We can't address 8 and 16 bit words directly. Instead we have to
101 * read/write a 32bit word and mask/modify the data we actually want. 101 * read/write a 32bit word and mask/modify the data we actually want.
102 */ 102 */
103static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn, 103static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
104 int where, int size, u32 * val) 104 int where, int size, u32 * val)
105{ 105{
106 u32 data = 0; 106 u32 data = 0;
107 107
108 if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 108 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
109 &data)) 109 where, &data))
110 return PCIBIOS_DEVICE_NOT_FOUND; 110 return PCIBIOS_DEVICE_NOT_FOUND;
111 111
112 if (size == 1) 112 if (size == 1)
@@ -119,16 +119,16 @@ static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn,
119 return PCIBIOS_SUCCESSFUL; 119 return PCIBIOS_SUCCESSFUL;
120} 120}
121 121
122static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn, 122static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
123 int where, int size, u32 val) 123 int where, int size, u32 val)
124{ 124{
125 u32 data = 0; 125 u32 data = 0;
126 126
127 if (size == 4) 127 if (size == 4)
128 data = val; 128 data = val;
129 else { 129 else {
130 if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 130 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
131 where, &data)) 131 devfn, where, &data))
132 return PCIBIOS_DEVICE_NOT_FOUND; 132 return PCIBIOS_DEVICE_NOT_FOUND;
133 133
134 if (size == 1) 134 if (size == 1)
@@ -139,14 +139,14 @@ static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn,
139 (val << ((where & 3) << 3)); 139 (val << ((where & 3) << 3));
140 } 140 }
141 141
142 if (gt64120_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, 142 if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
143 &data)) 143 where, &data))
144 return PCIBIOS_DEVICE_NOT_FOUND; 144 return PCIBIOS_DEVICE_NOT_FOUND;
145 145
146 return PCIBIOS_SUCCESSFUL; 146 return PCIBIOS_SUCCESSFUL;
147} 147}
148 148
149struct pci_ops gt64120_pci_ops = { 149struct pci_ops gt64xxx_pci0_ops = {
150 .read = gt64120_pcibios_read, 150 .read = gt64xxx_pci0_pcibios_read,
151 .write = gt64120_pcibios_write 151 .write = gt64xxx_pci0_pcibios_write
152}; 152};
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index 88fb191ad2eb..985784a3e6f8 100644
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -12,7 +12,7 @@
12#include <asm/bootinfo.h> 12#include <asm/bootinfo.h>
13 13
14extern struct pci_ops nile4_pci_ops; 14extern struct pci_ops nile4_pci_ops;
15extern struct pci_ops gt64120_pci_ops; 15extern struct pci_ops gt64xxx_pci0_ops;
16static struct resource lasat_pci_mem_resource = { 16static struct resource lasat_pci_mem_resource = {
17 .name = "LASAT PCI MEM", 17 .name = "LASAT PCI MEM",
18 .start = 0x18000000, 18 .start = 0x18000000,
@@ -38,7 +38,7 @@ static int __init lasat_pci_setup(void)
38 38
39 switch (mips_machtype) { 39 switch (mips_machtype) {
40 case MACH_LASAT_100: 40 case MACH_LASAT_100:
41 lasat_pci_controller.pci_ops = &gt64120_pci_ops; 41 lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
42 break; 42 break;
43 case MACH_LASAT_200: 43 case MACH_LASAT_200:
44 lasat_pci_controller.pci_ops = &nile4_pci_ops; 44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c
index 2b9495dce6ba..7f94f26d35ae 100644
--- a/arch/mips/pci/pci-ocelot.c
+++ b/arch/mips/pci/pci-ocelot.c
@@ -81,7 +81,7 @@ static struct resource ocelot_io_resource = {
81}; 81};
82 82
83static struct pci_controller ocelot_pci_controller = { 83static struct pci_controller ocelot_pci_controller = {
84 .pci_ops = gt64120_pci_ops; 84 .pci_ops = gt64xxx_pci0_ops;
85 .mem_resource = &ocelot_mem_resource; 85 .mem_resource = &ocelot_mem_resource;
86 .io_resource = &ocelot_io_resource; 86 .io_resource = &ocelot_io_resource;
87}; 87};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 05:28:32 -0500