Fixes for system controllers for Atlas/Malta core cards.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 13 insertions, 42 deletions

diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 4b4e086a7eb1..dc35270b65a2 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -17,7 +19,6 @@
  *
  * MIPS boards specific PCI support.
  */
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
@@ -57,13 +58,6 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
                 return -1;
         }
 
-#ifdef CONFIG_MIPS_BOARDS_GEN
-        if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
-                /* MIPS Core boards have Bonito connected as device 17 */
-                return -1;
-        }
-#endif
-
         /* Clear cause register bits */
         BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR |
                           BONITO_PCICMD_MTABORT_CLR);
diff --git a/arch/mips/pci/ops-gt64120.c b/arch/mips/pci/ops-gt64120.c
index 7b99dfa33dfc..6335844d607a 100644
--- a/arch/mips/pci/ops-gt64120.c
+++ b/arch/mips/pci/ops-gt64120.c
@@ -1,6 +1,8 @@
 /*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
+ *      All rights reserved.
+ *      Authors: Carsten Langgaard <carstenl@mips.com>
+ *               Maciej W. Rozycki <macro@mips.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
@@ -43,10 +45,6 @@ static int gt64120_pcibios_config_access(unsigned char access_type,
         unsigned char busnum = bus->number;
         u32 intr;
 
-        if ((busnum == 0) && (PCI_SLOT(devfn) == 0))
-                /* Galileo itself is devfn 0, don't move it around */
-                return -1;
-
         if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
                 return -1;      /* Because of a bug in the galileo (for slot 31). */
 
diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 7bc099643a9d..5d9fbb0f4670 100644
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -21,7 +21,6 @@
  * MIPS boards specific PCI support.
  *
  */
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/kernel.h>
@@ -49,34 +48,17 @@ static int msc_pcibios_config_access(unsigned char access_type,
         struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
 {
         unsigned char busnum = bus->number;
-        unsigned char type;
         u32 intr;
 
-#ifdef CONFIG_MIPS_BOARDS_GEN
-        if ((busnum == 0) && (PCI_SLOT(devfn) == 17)) {
-                /* MIPS Core boards have SOCit connected as device 17 */
-                return -1;
-        }
-#endif
-
         /* Clear status register bits. */
         MSC_WRITE(MSC01_PCI_INTSTAT,
                   (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
 
-        /* Setup address */
-        if (busnum == 0)
-                type = 0;       /* Type 0 */
-        else
-                type = 1;       /* Type 1 */
-
         MSC_WRITE(MSC01_PCI_CFGADDR,
                   ((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
-                   (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF)
-                   | (PCI_FUNC(devfn) <<
-                      MSC01_PCI_CFGADDR_FNUM_SHF) | ((where /
-                                                      4) <<
-                                                     MSC01_PCI_CFGADDR_RNUM_SHF)
-                   | (type)));
+                   (PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
+                   (PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
+                   ((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
 
         /* Perform access */
         if (access_type == PCI_ACCESS_WRITE)
@@ -86,15 +68,12 @@ static int msc_pcibios_config_access(unsigned char access_type,
 
         /* Detect Master/Target abort */
         MSC_READ(MSC01_PCI_INTSTAT, intr);
-        if (intr & (MSC01_PCI_INTCFG_MA_BIT |
-                    MSC01_PCI_INTCFG_TA_BIT)) {
+        if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
                 /* Error occurred */
 
                 /* Clear bits */
-                MSC_READ(MSC01_PCI_INTSTAT, intr);
                 MSC_WRITE(MSC01_PCI_INTSTAT,
-                          (MSC01_PCI_INTCFG_MA_BIT |
-                           MSC01_PCI_INTCFG_TA_BIT));
+                          (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
 
                 return -1;
         }