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authorRalf Baechle <ralf@linux-mips.org>2007-03-20 09:56:50 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-03-24 13:01:49 -0400
commit7605b3906192a171e651076325b1ed1d5ea57ec9 (patch)
treea86d308b36fda5297349691089a868208a5a9688 /arch/mips/pci
parent83598f1cb06101e972b1f5aaf3408eb729622fa8 (diff)
[MIPS] Fix pipeline hazard.
In the the sequence: ei .. mfc0 $x, $status the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the kernel code because we knew this was a safe thing to do on all R2 silicon so far but new silicon is changing this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
0 files changed, 0 insertions, 0 deletions