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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2006-06-13 07:59:01 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-19 12:39:24 -0400
commit4a0312fca6599299bbed944ce09278d90388a3e5 (patch)
treecde9b9d353eab1aa7ab062c2a958986bd45c1f24 /arch/mips/pci
parentb00f473e1af9a11454e572de1ea446eb672e700d (diff)
[MIPS] Support SNI RM200C SNI in big endian mode and R5000 processors.
Added support for RM200C machines with big endian firmware Added support for RM200-C40 (R5000 support) Signed-off-by: Florian Lohoff <flo@rfc822.org> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/ops-sni.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index 62bdd19c7f8e..2b0ccd6d9dcd 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -47,13 +47,13 @@ static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg,
47 47
48 switch (size) { 48 switch (size) {
49 case 1: 49 case 1:
50 *val = *(volatile u8 *) (PCIMT_CONFIG_DATA + (reg & 3)); 50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
51 break; 51 break;
52 case 2: 52 case 2:
53 *val = *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)); 53 *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
54 break; 54 break;
55 case 4: 55 case 4:
56 *val = *(volatile u32 *) PCIMT_CONFIG_DATA; 56 *val = inl(PCIMT_CONFIG_DATA);
57 break; 57 break;
58 } 58 }
59 59
@@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
70 70
71 switch (size) { 71 switch (size) {
72 case 1: 72 case 1:
73 *(volatile u8 *) (PCIMT_CONFIG_DATA + (reg & 3)) = val; 73 outb (val, PCIMT_CONFIG_DATA + (reg & 3));
74 break; 74 break;
75 case 2: 75 case 2:
76 *(volatile u16 *) (PCIMT_CONFIG_DATA + (reg & 2)) = val; 76 outw (val, PCIMT_CONFIG_DATA + (reg & 2));
77 break; 77 break;
78 case 4: 78 case 4:
79 *(volatile u32 *) PCIMT_CONFIG_DATA = val; 79 outl (val, PCIMT_CONFIG_DATA);
80 break; 80 break;
81 } 81 }
82 82