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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-10-02 10:19:00 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-10-03 12:59:17 -0400
commitaf8b128719f5248e542036ea994610a29d0642a6 (patch)
tree1330f156553cba8bccc9132c6a64bf766ed9ca8e /arch/mips/pci
parent08dfcee84c5c747ca1cecbd04c3a7e65cc9ce26b (diff)
[MIPS] Remove IT8172-based platforms, ITE 8172G and Globespan IVR support.
As per feature-removal-schedule.txt. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Acked-by: Alan Cox <alan@redhat.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/Makefile3
-rw-r--r--arch/mips/pci/fixup-ite8172g.c80
-rw-r--r--arch/mips/pci/fixup-ivr.c75
-rw-r--r--arch/mips/pci/ops-it8172.c213
4 files changed, 0 insertions, 371 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index edefa97b2330..3cf0dd4ba548 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -7,7 +7,6 @@ obj-y += pci.o
7# 7#
8# PCI bus host bridge specific code 8# PCI bus host bridge specific code
9# 9#
10obj-$(CONFIG_ITE_BOARD_GEN) += ops-it8172.o
11obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
12obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o 11obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o
13obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o 12obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o
@@ -28,8 +27,6 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
28obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 27obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
29obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 28obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
30obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o 29obj-$(CONFIG_MIPS_EV64120) += fixup-ev64120.o
31obj-$(CONFIG_MIPS_ITE8172) += fixup-ite8172g.o
32obj-$(CONFIG_MIPS_IVR) += fixup-ivr.o
33obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 30obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
34obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 31obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
35obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 32obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
diff --git a/arch/mips/pci/fixup-ite8172g.c b/arch/mips/pci/fixup-ite8172g.c
deleted file mode 100644
index 2290ea4228dd..000000000000
--- a/arch/mips/pci/fixup-ite8172g.c
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Board specific pci fixups.
4 *
5 * Copyright 2000 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/types.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/it8172/it8172.h>
35#include <asm/it8172/it8172_pci.h>
36#include <asm/it8172/it8172_int.h>
37
38/*
39 * Shortcuts
40 */
41#define INTA IT8172_PCI_INTA_IRQ
42#define INTB IT8172_PCI_INTB_IRQ
43#define INTC IT8172_PCI_INTC_IRQ
44#define INTD IT8172_PCI_INTD_IRQ
45
46static const int internal_func_irqs[7] __initdata = {
47 IT8172_AC97_IRQ,
48 IT8172_DMA_IRQ,
49 IT8172_CDMA_IRQ,
50 IT8172_USB_IRQ,
51 IT8172_BRIDGE_MASTER_IRQ,
52 IT8172_IDE_IRQ,
53 IT8172_MC68K_IRQ
54};
55
56static char irq_tab_ite8172g[][5] __initdata = {
57 [0x10] = { 0, INTA, INTB, INTC, INTD },
58 [0x11] = { 0, INTA, INTB, INTC, INTD },
59 [0x12] = { 0, INTB, INTC, INTD, INTA },
60 [0x13] = { 0, INTC, INTD, INTA, INTB },
61 [0x14] = { 0, INTD, INTA, INTB, INTC },
62};
63
64int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
65{
66 /*
67 * Internal device 1 is actually 7 different internal devices on the
68 * IT8172G (a multifunction device).
69 */
70 if (slot == 1)
71 return internal_func_irqs[PCI_FUNC(dev->devfn)];
72
73 return irq_tab_ite8172g[slot][pin];
74}
75
76/* Do platform specific device initialization at pci_enable_device() time */
77int pcibios_plat_dev_init(struct pci_dev *dev)
78{
79 return 0;
80}
diff --git a/arch/mips/pci/fixup-ivr.c b/arch/mips/pci/fixup-ivr.c
deleted file mode 100644
index 0c7c16464c11..000000000000
--- a/arch/mips/pci/fixup-ivr.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Globespan IVR board-specific pci fixups.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30#include <linux/types.h>
31#include <linux/pci.h>
32#include <linux/kernel.h>
33#include <linux/init.h>
34
35#include <asm/it8172/it8172.h>
36#include <asm/it8172/it8172_pci.h>
37#include <asm/it8172/it8172_int.h>
38
39/*
40 * Shortcuts
41 */
42#define INTA IT8172_PCI_INTA_IRQ
43#define INTB IT8172_PCI_INTB_IRQ
44#define INTC IT8172_PCI_INTC_IRQ
45#define INTD IT8172_PCI_INTD_IRQ
46
47static const int internal_func_irqs[7] __initdata = {
48 IT8172_AC97_IRQ,
49 IT8172_DMA_IRQ,
50 IT8172_CDMA_IRQ,
51 IT8172_USB_IRQ,
52 IT8172_BRIDGE_MASTER_IRQ,
53 IT8172_IDE_IRQ,
54 IT8172_MC68K_IRQ
55};
56
57static char irq_tab_ivr[][5] __initdata = {
58 [0x11] = { INTC, INTC, INTD, INTA, INTB }, /* Realtek RTL-8139 */
59 [0x12] = { INTB, INTB, INTB, INTC, INTC }, /* IVR slot */
60 [0x13] = { INTA, INTA, INTB, INTC, INTD } /* Expansion slot */
61};
62
63int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
64{
65 if (slot == 1)
66 return internal_func_irqs[PCI_FUNC(dev->devfn)];
67
68 return irq_tab_ivr[slot][pin];
69}
70
71/* Do platform specific device initialization at pci_enable_device() time */
72int pcibios_plat_dev_init(struct pci_dev *dev)
73{
74 return 0;
75}
diff --git a/arch/mips/pci/ops-it8172.c b/arch/mips/pci/ops-it8172.c
deleted file mode 100644
index ba8328505a0a..000000000000
--- a/arch/mips/pci/ops-it8172.c
+++ /dev/null
@@ -1,213 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 system controller specific pci support.
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * ppopov@mvista.com or source@mvista.com
9 *
10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/kernel.h>
35#include <linux/init.h>
36
37#include <asm/it8172/it8172.h>
38#include <asm/it8172/it8172_pci.h>
39
40#define PCI_ACCESS_READ 0
41#define PCI_ACCESS_WRITE 1
42
43#undef DEBUG
44#ifdef DEBUG
45#define DBG(x...) printk(x)
46#else
47#define DBG(x...)
48#endif
49
50static struct resource pci_mem_resource_1;
51
52static struct resource pci_io_resource = {
53 .start = 0x14018000,
54 .end = 0x17FFFFFF,
55 .name = "io pci IO space",
56 .flags = IORESOURCE_IO
57};
58
59static struct resource pci_mem_resource_0 = {
60 .start = 0x10101000,
61 .end = 0x13FFFFFF,
62 .name = "ext pci memory space 0/1",
63 .flags = IORESOURCE_MEM,
64 .parent = &pci_mem_resource_0,
65 .sibling = NULL,
66 .child = &pci_mem_resource_1
67};
68
69static struct resource pci_mem_resource_1 = {
70 .start = 0x1A000000,
71 .end = 0x1FBFFFFF,
72 .name = "ext pci memory space 2/3",
73 .flags = IORESOURCE_MEM,
74 .parent = &pci_mem_resource_0
75};
76
77extern struct pci_ops it8172_pci_ops;
78
79struct pci_controller it8172_controller = {
80 .pci_ops = &it8172_pci_ops,
81 .io_resource = &pci_io_resource,
82 .mem_resource = &pci_mem_resource_0,
83};
84
85static int it8172_pcibios_config_access(unsigned char access_type,
86 struct pci_bus *bus,
87 unsigned int devfn, int where,
88 u32 * data)
89{
90 /*
91 * config cycles are on 4 byte boundary only
92 */
93
94 /* Setup address */
95 IT_WRITE(IT_CONFADDR, (bus->number << IT_BUSNUM_SHF) |
96 (devfn << IT_FUNCNUM_SHF) | (where & ~0x3));
97
98 if (access_type == PCI_ACCESS_WRITE) {
99 IT_WRITE(IT_CONFDATA, *data);
100 } else {
101 IT_READ(IT_CONFDATA, *data);
102 }
103
104 /*
105 * Revisit: check for master or target abort.
106 */
107 return 0;
108}
109
110
111/*
112 * We can't address 8 and 16 bit words directly. Instead we have to
113 * read/write a 32bit word and mask/modify the data we actually want.
114 */
115static write_config(struct pci_bus *bus, unsigned int devfn, int where,
116 int size, u32 val)
117{
118 u32 data = 0;
119
120 switch (size) {
121 case 1:
122 if (it8172_pcibios_config_access
123 (PCI_ACCESS_READ, dev, where, &data))
124 return -1;
125
126 *val = (data >> ((where & 3) << 3)) & 0xff;
127
128 return PCIBIOS_SUCCESSFUL;
129
130 case 2:
131
132 if (where & 1)
133 return PCIBIOS_BAD_REGISTER_NUMBER;
134
135 if (it8172_pcibios_config_access
136 (PCI_ACCESS_READ, dev, where, &data))
137 return -1;
138
139 *val = (data >> ((where & 3) << 3)) & 0xffff;
140 DBG("cfg read word: bus %d dev_fn %x where %x: val %x\n",
141 dev->bus->number, dev->devfn, where, *val);
142
143 return PCIBIOS_SUCCESSFUL;
144
145 case 4:
146
147 if (where & 3)
148 return PCIBIOS_BAD_REGISTER_NUMBER;
149
150 if (it8172_pcibios_config_access
151 (PCI_ACCESS_READ, dev, where, &data))
152 return -1;
153
154 *val = data;
155
156 return PCIBIOS_SUCCESSFUL;
157 }
158}
159
160
161static write_config(struct pci_bus *bus, unsigned int devfn, int where,
162 int size, u32 val)
163{
164 u32 data = 0;
165
166 switch (size) {
167 case 1:
168 if (it8172_pcibios_config_access
169 (PCI_ACCESS_READ, dev, where, &data))
170 return -1;
171
172 data = (data & ~(0xff << ((where & 3) << 3))) |
173 (val << ((where & 3) << 3));
174
175 if (it8172_pcibios_config_access
176 (PCI_ACCESS_WRITE, dev, where, &data))
177 return -1;
178
179 return PCIBIOS_SUCCESSFUL;
180
181 case 2:
182 if (where & 1)
183 return PCIBIOS_BAD_REGISTER_NUMBER;
184
185 if (it8172_pcibios_config_access
186 (PCI_ACCESS_READ, dev, where, &data))
187 eturn - 1;
188
189 data = (data & ~(0xffff << ((where & 3) << 3))) |
190 (val << ((where & 3) << 3));
191
192 if (it8172_pcibios_config_access
193 (PCI_ACCESS_WRITE, dev, where, &data))
194 return -1;
195
196 return PCIBIOS_SUCCESSFUL;
197
198 case 4:
199 if (where & 3)
200 return PCIBIOS_BAD_REGISTER_NUMBER;
201
202 if (it8172_pcibios_config_access
203 (PCI_ACCESS_WRITE, dev, where, &val))
204 return -1;
205
206 return PCIBIOS_SUCCESSFUL;
207 }
208}
209
210struct pci_ops it8172_pci_ops = {
211 .read = read_config,
212 .write = write_config,
213};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-08 23:25:08 -0500