Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "The whole series has been sitting in -next for quite a while with no
  complaints.  The last change to the series was before the weekend the
  removal of an SPI patch which Grant - even though previously acked by
  himself - appeared to raise objections.  So I removed it until the
  situation is clarified.  Other than that all the patches have the acks
  from their respective maintainers, all MIPS and x86 defconfigs are
  building fine and I'm not aware of any problems introduced by this
  series.

  Among the key features for this patch series is a sizable patchset for
  Lantiq which among other things introduces support for Lantiq's
  flagship product, the FALCON SOC.  It also means that the opensource
  developers behind this patchset have overtaken Lantiq's competing
  inhouse development team that was working behind closed doors.

  Less noteworthy the ath79 patchset which adds support for a few more
  chip variants, cleanups and fixes.  Finally the usual dose of tweaking
  of generic code."

Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where
printk spelling fixes clashed with file move and eventual removal of the
printk.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits)
  MIPS: lantiq: remove orphaned code
  MIPS: Remove all -Wall and almost all -Werror usage from arch/mips.
  MIPS: lantiq: implement support for FALCON soc
  MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc
  MTD: MIPS: lantiq: implement OF support
  watchdog: MIPS: lantiq: implement OF support and minor fixes
  SERIAL: MIPS: lantiq: implement OF support
  GPIO: MIPS: lantiq: convert gpio-stp-xway to OF
  GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio
  GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder
  MIPS: pci: convert lantiq driver to OF
  MIPS: lantiq: convert dma to platform driver
  MIPS: lantiq: implement support for clkdev api
  MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq()
  OF: MIPS: lantiq: implement irq_domain support
  OF: MIPS: lantiq: implement OF support
  MIPS: lantiq: drop mips_machine support
  OF: PCI: const usage needed by MIPS
  MIPS: Cavium: Remove smp_reserve_lock.
  MIPS: Move cache setup to setup_arch().
  ...

1 files changed, 55 insertions, 0 deletions

diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 0514866fa925..271e8c4a54c7 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
+#include <linux/of_address.h>
 
 #include <asm/cpu-info.h>
 
@@ -114,9 +115,63 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
                         pci_bus_assign_resources(bus);
                         pci_enable_bridges(bus);
                 }
+                bus->dev.of_node = hose->of_node;
         }
 }
 
+#ifdef CONFIG_OF
+void __devinit pci_load_of_ranges(struct pci_controller *hose,
+                                struct device_node *node)
+{
+        const __be32 *ranges;
+        int rlen;
+        int pna = of_n_addr_cells(node);
+        int np = pna + 5;
+
+        pr_info("PCI host bridge %s ranges:\n", node->full_name);
+        ranges = of_get_property(node, "ranges", &rlen);
+        if (ranges == NULL)
+                return;
+        hose->of_node = node;
+
+        while ((rlen -= np * 4) >= 0) {
+                u32 pci_space;
+                struct resource *res = NULL;
+                u64 addr, size;
+
+                pci_space = be32_to_cpup(&ranges[0]);
+                addr = of_translate_address(node, ranges + 3);
+                size = of_read_number(ranges + pna + 3, 2);
+                ranges += np;
+                switch ((pci_space >> 24) & 0x3) {
+                case 1:         /* PCI IO space */
+                        pr_info("  IO 0x%016llx..0x%016llx\n",
+                                        addr, addr + size - 1);
+                        hose->io_map_base =
+                                (unsigned long)ioremap(addr, size);
+                        res = hose->io_resource;
+                        res->flags = IORESOURCE_IO;
+                        break;
+                case 2:         /* PCI Memory space */
+                case 3:         /* PCI 64 bits Memory space */
+                        pr_info(" MEM 0x%016llx..0x%016llx\n",
+                                        addr, addr + size - 1);
+                        res = hose->mem_resource;
+                        res->flags = IORESOURCE_MEM;
+                        break;
+                }
+                if (res != NULL) {
+                        res->start = addr;
+                        res->name = node->full_name;
+                        res->end = res->start + size - 1;
+                        res->parent = NULL;
+                        res->sibling = NULL;
+                        res->child = NULL;
+                }
+        }
+}
+#endif
+
 static DEFINE_MUTEX(pci_scan_mutex);
 
 void __devinit register_pci_controller(struct pci_controller *hose)