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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-03-02 10:44:16 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-03-02 10:44:16 -0500 |
commit | aebb2afd5420c860b7fbc3882a323ef1247fbf16 (patch) | |
tree | 05ee0efcebca5ec421de44de7a6d6271088c64a8 /arch/mips/pci/pci-xlr.c | |
parent | 8eae508b7c6ff502a71d0293b69e97c5505d5840 (diff) | |
parent | edb15d83a875a1f4b1576188844db5c330c3267d (diff) |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
o Add basic support for the Mediatek/Ralink Wireless SoC family.
o The Qualcomm Atheros platform is extended by support for the new
QCA955X SoC series as well as a bunch of patches that get the code
ready for OF support.
o Lantiq and BCM47XX platform have a few improvements and bug fixes.
o MIPS has sent a few patches that get the kernel ready for the
upcoming microMIPS support.
o The rest of the series is made up of small bug fixes and cleanups
that relate to various parts of the MIPS code. The biggy in there is
a whitespace cleanup. After I was sent another set of whitespace
cleanup patches I decided it was the time to clean the whitespace
"issues" for once and and that touches many files below arch/mips/.
Fix up silly conflicts, mostly due to whitespace cleanups.
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
MIPS: remove broken conditional inside vpe loader code
MIPS: SMTC: fix implicit declaration of set_vi_handler
MIPS: early_printk: drop __init annotations
MIPS: Probe for and report hardware virtualization support.
MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
MIPS: ath79: add USB controller registration code for the QCA955X SoCs
MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
MIPS: ath79: add WMAC registration code for the QCA955X SoCs
MIPS: ath79: register UART for the QCA955X SoCs
MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
MIPS: ath79: add GPIO setup code for the QCA955X SoCs
MIPS: ath79: add IRQ handling code for the QCA955X SoCs
MIPS: ath79: add clock setup code for the QCA955X SoCs
MIPS: ath79: add SoC detection code for the QCA955X SoCs
MIPS: ath79: add early printk support for the QCA955X SoCs
MIPS: ath79: fix WMAC IRQ resource assignment
mips: reserve elfcorehdr
mips: Make sure kernel memory is in iomem
MIPS: ath79: use dynamically allocated USB platform devices
...
Diffstat (limited to 'arch/mips/pci/pci-xlr.c')
-rw-r--r-- | arch/mips/pci/pci-xlr.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 0c18ccc79623..4427abbd48b5 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c | |||
@@ -56,7 +56,7 @@ | |||
56 | 56 | ||
57 | static void *pci_config_base; | 57 | static void *pci_config_base; |
58 | 58 | ||
59 | #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) | 59 | #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) |
60 | 60 | ||
61 | /* PCI ops */ | 61 | /* PCI ops */ |
62 | static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, | 62 | static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, |
@@ -136,26 +136,26 @@ struct pci_ops nlm_pci_ops = { | |||
136 | }; | 136 | }; |
137 | 137 | ||
138 | static struct resource nlm_pci_mem_resource = { | 138 | static struct resource nlm_pci_mem_resource = { |
139 | .name = "XLR PCI MEM", | 139 | .name = "XLR PCI MEM", |
140 | .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ | 140 | .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ |
141 | .end = 0xdfffffffUL, | 141 | .end = 0xdfffffffUL, |
142 | .flags = IORESOURCE_MEM, | 142 | .flags = IORESOURCE_MEM, |
143 | }; | 143 | }; |
144 | 144 | ||
145 | static struct resource nlm_pci_io_resource = { | 145 | static struct resource nlm_pci_io_resource = { |
146 | .name = "XLR IO MEM", | 146 | .name = "XLR IO MEM", |
147 | .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ | 147 | .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ |
148 | .end = 0x100fffffUL, | 148 | .end = 0x100fffffUL, |
149 | .flags = IORESOURCE_IO, | 149 | .flags = IORESOURCE_IO, |
150 | }; | 150 | }; |
151 | 151 | ||
152 | struct pci_controller nlm_pci_controller = { | 152 | struct pci_controller nlm_pci_controller = { |
153 | .index = 0, | 153 | .index = 0, |
154 | .pci_ops = &nlm_pci_ops, | 154 | .pci_ops = &nlm_pci_ops, |
155 | .mem_resource = &nlm_pci_mem_resource, | 155 | .mem_resource = &nlm_pci_mem_resource, |
156 | .mem_offset = 0x00000000UL, | 156 | .mem_offset = 0x00000000UL, |
157 | .io_resource = &nlm_pci_io_resource, | 157 | .io_resource = &nlm_pci_io_resource, |
158 | .io_offset = 0x00000000UL, | 158 | .io_offset = 0x00000000UL, |
159 | }; | 159 | }; |
160 | 160 | ||
161 | /* | 161 | /* |
@@ -259,7 +259,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | |||
259 | MSI_ADDR_REDIRECTION_CPU; | 259 | MSI_ADDR_REDIRECTION_CPU; |
260 | 260 | ||
261 | msg.data = MSI_DATA_TRIGGER_EDGE | | 261 | msg.data = MSI_DATA_TRIGGER_EDGE | |
262 | MSI_DATA_LEVEL_ASSERT | | 262 | MSI_DATA_LEVEL_ASSERT | |
263 | MSI_DATA_DELIVERY_FIXED; | 263 | MSI_DATA_DELIVERY_FIXED; |
264 | 264 | ||
265 | ret = irq_set_msi_desc(irq, desc); | 265 | ret = irq_set_msi_desc(irq, desc); |
@@ -344,7 +344,7 @@ static int __init pcibios_init(void) | |||
344 | pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); | 344 | pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); |
345 | 345 | ||
346 | /* Extend IO port for memory mapped io */ | 346 | /* Extend IO port for memory mapped io */ |
347 | ioport_resource.start = 0; | 347 | ioport_resource.start = 0; |
348 | ioport_resource.end = ~0; | 348 | ioport_resource.end = ~0; |
349 | 349 | ||
350 | set_io_port_base(CKSEG1); | 350 | set_io_port_base(CKSEG1); |