[MIPS] TXx9: Reorganize PCI code

Split out PCIC dependent code and SoC dependent code from board dependent
code.  Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code.
Also fix some build problems on CONFIG_PCI=n.

As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards
and PCI66 support is available for all TX49 boards.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 83 insertions, 0 deletions

diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
new file mode 100644
index 000000000000..27e86a09dd41
--- /dev/null
+++ b/arch/mips/pci/pci-tx4927.c
@@ -0,0 +1,83 @@
+/*
+ * linux/arch/mips/pci/pci-tx4927.c
+ *
+ * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
+ *          and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4927.h>
+
+int __init tx4927_report_pciclk(void)
+{
+        int pciclk = 0;
+
+        printk(KERN_INFO "PCIC --%s PCICLK:",
+               (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
+               " PCI66" : "");
+        if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
+                u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
+                switch ((unsigned long)ccfg &
+                        TX4927_CCFG_PCIDIVMODE_MASK) {
+                case TX4927_CCFG_PCIDIVMODE_2_5:
+                        pciclk = txx9_cpu_clock * 2 / 5; break;
+                case TX4927_CCFG_PCIDIVMODE_3:
+                        pciclk = txx9_cpu_clock / 3; break;
+                case TX4927_CCFG_PCIDIVMODE_5:
+                        pciclk = txx9_cpu_clock / 5; break;
+                case TX4927_CCFG_PCIDIVMODE_6:
+                        pciclk = txx9_cpu_clock / 6; break;
+                }
+                printk("Internal(%u.%uMHz)",
+                       (pciclk + 50000) / 1000000,
+                       ((pciclk + 50000) / 100000) % 10);
+        } else {
+                printk("External");
+                pciclk = -1;
+        }
+        printk("\n");
+        return pciclk;
+}
+
+int __init tx4927_pciclk66_setup(void)
+{
+        int pciclk;
+
+        /* Assert M66EN */
+        tx4927_ccfg_set(TX4927_CCFG_PCI66);
+        /* Double PCICLK (if possible) */
+        if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
+                unsigned int pcidivmode = 0;
+                u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
+                pcidivmode = (unsigned long)ccfg &
+                        TX4927_CCFG_PCIDIVMODE_MASK;
+                switch (pcidivmode) {
+                case TX4927_CCFG_PCIDIVMODE_5:
+                case TX4927_CCFG_PCIDIVMODE_2_5:
+                        pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
+                        pciclk = txx9_cpu_clock * 2 / 5;
+                        break;
+                case TX4927_CCFG_PCIDIVMODE_6:
+                case TX4927_CCFG_PCIDIVMODE_3:
+                default:
+                        pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
+                        pciclk = txx9_cpu_clock / 3;
+                }
+                tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
+                                   pcidivmode);
+                printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
+                       (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
+        } else
+                pciclk = -1;
+        return pciclk;
+}