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authorRalf Baechle <ralf@linux-mips.org>2006-03-11 03:18:41 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-03-21 08:27:47 -0500
commita3dddd560ee936495466d85ecc97490d171e8d31 (patch)
treee9b5d778b5249ce348d2285a9b886b83c510d813 /arch/mips/pci/pci-ip27.c
parent59b3e8e9aac69d2d02853acac7e2affdfbabca50 (diff)
[MIPS] War on whitespace: cleanup initial spaces followed by tabs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/pci-ip27.c')
-rw-r--r--arch/mips/pci/pci-ip27.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index efc96ce99eeb..6002d2a6a262 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -379,18 +379,18 @@ int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid)
379 bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id); 379 bridge = (bridge_t *) RAW_NODE_SWIN_BASE(nasid, widget_id);
380 380
381 /* 381 /*
382 * Clear all pending interrupts. 382 * Clear all pending interrupts.
383 */ 383 */
384 bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR; 384 bridge->b_int_rst_stat = BRIDGE_IRR_ALL_CLR;
385 385
386 /* 386 /*
387 * Until otherwise set up, assume all interrupts are from slot 0 387 * Until otherwise set up, assume all interrupts are from slot 0
388 */ 388 */
389 bridge->b_int_device = 0x0; 389 bridge->b_int_device = 0x0;
390 390
391 /* 391 /*
392 * swap pio's to pci mem and io space (big windows) 392 * swap pio's to pci mem and io space (big windows)
393 */ 393 */
394 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP | 394 bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
395 BRIDGE_CTRL_MEM_SWAP; 395 BRIDGE_CTRL_MEM_SWAP;
396 396