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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2008-01-05 06:13:11 -0500
committerRalf Baechle <ralf@linux-mips.org>2008-01-07 10:32:03 -0500
commitc990081bf87bf5afcd6d39d8bfce9c6d60b1f2eb (patch)
treef1d87ded4fc653bcf0a35c24ea53b4fd18d4cbd4 /arch/mips/pci/ops-mace.c
parent9cfacb790f581000a7ec8455785d131aca923ded (diff)
[MIPS] Fix IP32 breakage
- suppress master aborts during config read - set io_map_base - only fixup end of iomem resource to avoid failing request_resource in serial driver - killed useless setting of crime_int bit, which caused wrong interrupts - use physcial address for serial port platform device and let 8250 driver do the ioremap Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/pci/ops-mace.c')
-rw-r--r--arch/mips/pci/ops-mace.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c
index fe5451449304..e95881897ec9 100644
--- a/arch/mips/pci/ops-mace.c
+++ b/arch/mips/pci/ops-mace.c
@@ -42,6 +42,10 @@ static int
42mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, 42mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
43 int reg, int size, u32 *val) 43 int reg, int size, u32 *val)
44{ 44{
45 u32 control = mace->pci.control;
46
47 /* disable master aborts interrupts during config read */
48 mace->pci.control = control & ~MACEPCI_CONTROL_MAR_INT;
45 mace->pci.config_addr = mkaddr(bus, devfn, reg); 49 mace->pci.config_addr = mkaddr(bus, devfn, reg);
46 switch (size) { 50 switch (size) {
47 case 1: 51 case 1:
@@ -54,6 +58,9 @@ mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
54 *val = mace->pci.config_data.l; 58 *val = mace->pci.config_data.l;
55 break; 59 break;
56 } 60 }
61 /* ack possible master abort */
62 mace->pci.error &= ~MACEPCI_ERROR_MASTER_ABORT;
63 mace->pci.control = control;
57 64
58 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val); 65 DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
59 66