[MIPS] Separate performance counter interrupts

Support for performance counter overflow interrupt that is on a separate
interrupt from the timer.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 5 insertions, 2 deletions

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 4f94fa261aae..1ea5c9c1010b 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -177,7 +177,10 @@ static int mipsxx_perfcount_handler(void)
         unsigned int counters = op_model_mipsxx_ops.num_counters;
         unsigned int control;
         unsigned int counter;
-        int handled = 0;
+        int handled = IRQ_NONE;
+
+        if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
+                return handled;
 
         switch (counters) {
 #define HANDLE_COUNTER(n)                                               \
@@ -188,7 +191,7 @@ static int mipsxx_perfcount_handler(void)
                     (counter & M_COUNTER_OVERFLOW)) {                   \
                         oprofile_add_sample(get_irq_regs(), n);         \
                         w_c0_perfcntr ## n(reg.counter[n]);             \
-                        handled = 1;                                    \
+                        handled = IRQ_HANDLED;                          \
                 }
         HANDLE_COUNTER(3)
         HANDLE_COUNTER(2)