diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2008-06-12 12:26:02 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-06-16 10:14:47 -0400 |
commit | 89052bd7b393434f7c573ce6a3b88c5f143586d2 (patch) | |
tree | e68bf4c2b46ca1c33b0fa1b78da6ea2a4db3aff4 /arch/mips/nxp | |
parent | 330117ff2723566e8eb7ad43223081b557f1540e (diff) |
[MIPS] Fix build for PNX platforms.
Build error was caused by commit 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/nxp')
-rw-r--r-- | arch/mips/nxp/pnx8550/jbs/board_setup.c | 11 | ||||
-rw-r--r-- | arch/mips/nxp/pnx8550/stb810/board_setup.c | 10 |
2 files changed, 2 insertions, 19 deletions
diff --git a/arch/mips/nxp/pnx8550/jbs/board_setup.c b/arch/mips/nxp/pnx8550/jbs/board_setup.c index f92826e0096d..57dd903ca408 100644 --- a/arch/mips/nxp/pnx8550/jbs/board_setup.c +++ b/arch/mips/nxp/pnx8550/jbs/board_setup.c | |||
@@ -47,16 +47,7 @@ | |||
47 | 47 | ||
48 | void __init board_setup(void) | 48 | void __init board_setup(void) |
49 | { | 49 | { |
50 | unsigned long config0, configpr; | 50 | unsigned long configpr; |
51 | |||
52 | config0 = read_c0_config(); | ||
53 | |||
54 | /* clear all three cache coherency fields */ | ||
55 | config0 &= ~(0x7 | (7<<25) | (7<<28)); | ||
56 | config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | | ||
57 | (CONF_CM_DEFAULT<<28)); | ||
58 | write_c0_config(config0); | ||
59 | BARRIER; | ||
60 | 51 | ||
61 | configpr = read_c0_config7(); | 52 | configpr = read_c0_config7(); |
62 | configpr |= (1<<19); /* enable tlb */ | 53 | configpr |= (1<<19); /* enable tlb */ |
diff --git a/arch/mips/nxp/pnx8550/stb810/board_setup.c b/arch/mips/nxp/pnx8550/stb810/board_setup.c index 1282c27cfcb7..af2a55e0b4e9 100644 --- a/arch/mips/nxp/pnx8550/stb810/board_setup.c +++ b/arch/mips/nxp/pnx8550/stb810/board_setup.c | |||
@@ -33,15 +33,7 @@ | |||
33 | 33 | ||
34 | void __init board_setup(void) | 34 | void __init board_setup(void) |
35 | { | 35 | { |
36 | unsigned long config0, configpr; | 36 | unsigned long configpr; |
37 | |||
38 | config0 = read_c0_config(); | ||
39 | |||
40 | /* clear all three cache coherency fields */ | ||
41 | config0 &= ~(0x7 | (7<<25) | (7<<28)); | ||
42 | config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | | ||
43 | (CONF_CM_DEFAULT<<28)); | ||
44 | write_c0_config(config0); | ||
45 | 37 | ||
46 | configpr = read_c0_config7(); | 38 | configpr = read_c0_config7(); |
47 | configpr |= (1<<19); /* enable tlb */ | 39 | configpr |= (1<<19); /* enable tlb */ |