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authorJayachandran C <jayachandranc@netlogicmicro.com>2012-07-24 11:26:34 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-24 11:26:34 -0400
commitcedc8ef87c3349a6645e285f920715380dd25ddc (patch)
treef50cfa5c0fed0b50289511c8c5dba51c57710483 /arch/mips/netlogic
parent28a33cbc24e4256c143dce96c7d93bf423229f92 (diff)
MIPS: Netlogic: Update comments in smpboot.S
No change in logic, comments update and whitespace cleanup. * A few comments in the file were in assembler style and the rest int C style, convert all of them to C style. * Mark workarounds for Ax silicon with a macro XLP_AX_WORKAROUND * Whitespace fixes - use tabs consistently * rename __config_lsu macro to xlp_config_lsu Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r--arch/mips/netlogic/common/smpboot.S106
1 files changed, 58 insertions, 48 deletions
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index c138b1a6dec3..c4872a714cfe 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -54,28 +54,36 @@
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57.macro __config_lsu 57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
58 li t0, LSU_DEFEATURE
59 mfcr t1, t0
60 58
61 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */ 59/* Enable XLP features and workarounds in the LSU */
62 or t1, t1, t2 60.macro xlp_config_lsu
63 li t2, ~0xe /* S1RCM */ 61 li t0, LSU_DEFEATURE
62 mfcr t1, t0
63
64 lui t2, 0x4080 /* Enable Unaligned Access, L2HPE */
65 or t1, t1, t2
66#ifdef XLP_AX_WORKAROUND
67 li t2, ~0xe /* S1RCM */
64 and t1, t1, t2 68 and t1, t1, t2
69#endif
65 mtcr t1, t0 70 mtcr t1, t0
66 71
67 li t0, SCHED_DEFEATURE 72#ifdef XLP_AX_WORKAROUND
68 lui t1, 0x0100 /* Experimental: Disable BRU accepting ALU ops */ 73 li t0, SCHED_DEFEATURE
69 mtcr t1, t0 74 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
75 mtcr t1, t0
76#endif
70.endm 77.endm
71 78
72/* 79/*
73 * The cores can come start when they are woken up. This is also the NMI 80 * This is the code that will be copied to the reset entry point for
74 * entry, so check that first. 81 * XLR and XLP. The XLP cores start here when they are woken up. This
82 * is also the NMI entry point.
75 * 83 *
76 * The data corresponding to reset is stored at RESET_DATA_PHYS location, 84 * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
77 * this will have the thread mask (used when core is woken up) and the 85 * location, this will have the thread mask (used when core is woken up)
78 * current NMI handler in case we reached here for an NMI. 86 * and the current NMI handler in case we reached here for an NMI.
79 * 87 *
80 * When a core or thread is newly woken up, it loops in a 'wait'. When 88 * When a core or thread is newly woken up, it loops in a 'wait'. When
81 * the CPU really needs waking up, we send an NMI to it, with the NMI 89 * the CPU really needs waking up, we send an NMI to it, with the NMI
@@ -89,12 +97,12 @@
89FEXPORT(nlm_reset_entry) 97FEXPORT(nlm_reset_entry)
90 dmtc0 k0, $22, 6 98 dmtc0 k0, $22, 6
91 dmtc0 k1, $22, 7 99 dmtc0 k1, $22, 7
92 mfc0 k0, CP0_STATUS 100 mfc0 k0, CP0_STATUS
93 li k1, 0x80000 101 li k1, 0x80000
94 and k1, k0, k1 102 and k1, k0, k1
95 beqz k1, 1f /* go to real reset entry */ 103 beqz k1, 1f /* go to real reset entry */
96 nop 104 nop
97 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */ 105 li k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
98 ld k0, BOOT_NMI_HANDLER(k1) 106 ld k0, BOOT_NMI_HANDLER(k1)
99 jr k0 107 jr k0
100 nop 108 nop
@@ -114,21 +122,23 @@ FEXPORT(nlm_reset_entry)
114 li t2, SYS_CPU_COHERENT_BASE(0) 122 li t2, SYS_CPU_COHERENT_BASE(0)
115 add t2, t2, t3 /* t2 <- SYS offset for node */ 123 add t2, t2, t3 /* t2 <- SYS offset for node */
116 lw t1, 0(t2) 124 lw t1, 0(t2)
117 and t1, t1, t0 125 and t1, t1, t0
118 sw t1, 0(t2) 126 sw t1, 0(t2)
119 127
120 /* read back to ensure complete */ 128 /* read back to ensure complete */
121 lw t1, 0(t2) 129 lw t1, 0(t2)
122 sync 130 sync
123 131
124 /* Configure LSU on Non-0 Cores. */ 132 /* Configure LSU on Non-0 Cores. */
125 __config_lsu 133 xlp_config_lsu
134 /* FALL THROUGH */
126 135
127/* 136/*
128 * Wake up sibling threads from the initial thread in 137 * Wake up sibling threads from the initial thread in
129 * a core. 138 * a core.
130 */ 139 */
131EXPORT(nlm_boot_siblings) 140EXPORT(nlm_boot_siblings)
141 /* Enable hw threads by writing to MAP_THREADMODE of the core */
132 li t0, CKSEG1ADDR(RESET_DATA_PHYS) 142 li t0, CKSEG1ADDR(RESET_DATA_PHYS)
133 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */ 143 lw t1, BOOT_THREAD_MODE(t0) /* t1 <- thread mode */
134 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE) 144 li t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
@@ -139,13 +149,14 @@ EXPORT(nlm_boot_siblings)
139 /* 149 /*
140 * The new hardware thread starts at the next instruction 150 * The new hardware thread starts at the next instruction
141 * For all the cases other than core 0 thread 0, we will 151 * For all the cases other than core 0 thread 0, we will
142 * jump to the secondary wait function. 152 * jump to the secondary wait function.
143 */ 153 */
144 mfc0 v0, CP0_EBASE, 1 154 mfc0 v0, CP0_EBASE, 1
145 andi v0, 0x7f /* v0 <- node/core */ 155 andi v0, 0x7f /* v0 <- node/core */
146 156
147#if 1 157 /* Init MMU in the first thread after changing THREAD_MODE
148 /* A0 errata - Write MMU_SETUP after changing thread mode register. */ 158 * register (Ax Errata?)
159 */
149 andi v1, v0, 0x3 /* v1 <- thread id */ 160 andi v1, v0, 0x3 /* v1 <- thread id */
150 bnez v1, 2f 161 bnez v1, 2f
151 nop 162 nop
@@ -154,9 +165,8 @@ EXPORT(nlm_boot_siblings)
154 li t1, 0 165 li t1, 0
155 mtcr t1, t0 166 mtcr t1, t0
156 ehb 167 ehb
157#endif
158 168
1592: beqz v0, 4f 1692: beqz v0, 4f /* boot cpu (cpuid == 0)? */
160 nop 170 nop
161 171
162 /* setup status reg */ 172 /* setup status reg */
@@ -183,9 +193,9 @@ EXPORT(nlm_boot_siblings)
183 * For the boot CPU, we have to restore registers and 193 * For the boot CPU, we have to restore registers and
184 * return 194 * return
185 */ 195 */
1864: dmfc0 t0, $4, 2 /* restore SP from UserLocal */ 1964: dmfc0 t0, $4, 2 /* restore SP from UserLocal */
187 li t1, 0xfadebeef 197 li t1, 0xfadebeef
188 dmtc0 t1, $4, 2 /* restore SP from UserLocal */ 198 dmtc0 t1, $4, 2 /* restore SP from UserLocal */
189 PTR_SUBU sp, t0, PT_SIZE 199 PTR_SUBU sp, t0, PT_SIZE
190 RESTORE_ALL 200 RESTORE_ALL
191 jr ra 201 jr ra
@@ -193,7 +203,7 @@ EXPORT(nlm_boot_siblings)
193EXPORT(nlm_reset_entry_end) 203EXPORT(nlm_reset_entry_end)
194 204
195FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */ 205FEXPORT(xlp_boot_core0_siblings) /* "Master" cpu starts from here */
196 __config_lsu 206 xlp_config_lsu
197 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 207 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
198 SAVE_ALL 208 SAVE_ALL
199 sync 209 sync
@@ -234,36 +244,36 @@ END(nlm_boot_secondary_cpus)
234 */ 244 */
235 __CPUINIT 245 __CPUINIT
236NESTED(nlm_rmiboot_preboot, 16, sp) 246NESTED(nlm_rmiboot_preboot, 16, sp)
237 mfc0 t0, $15, 1 # read ebase 247 mfc0 t0, $15, 1 /* read ebase */
238 andi t0, 0x1f # t0 has the processor_id() 248 andi t0, 0x1f /* t0 has the processor_id() */
239 andi t2, t0, 0x3 # thread no 249 andi t2, t0, 0x3 /* thread num */
240 sll t0, 2 # offset in cpu array 250 sll t0, 2 /* offset in cpu array */
241 251
242 PTR_LA t1, nlm_cpu_ready # mark CPU ready 252 PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
243 PTR_ADDU t1, t0 253 PTR_ADDU t1, t0
244 li t3, 1 254 li t3, 1
245 sw t3, 0(t1) 255 sw t3, 0(t1)
246 256
247 bnez t2, 1f # skip thread programming 257 bnez t2, 1f /* skip thread programming */
248 nop # for non zero hw threads 258 nop /* for thread id != 0 */
249 259
250 /* 260 /*
251 * MMU setup only for first thread in core 261 * XLR MMU setup only for first thread in core
252 */ 262 */
253 li t0, 0x400 263 li t0, 0x400
254 mfcr t1, t0 264 mfcr t1, t0
255 li t2, 6 # XLR thread mode mask 265 li t2, 6 /* XLR thread mode mask */
256 nor t3, t2, zero 266 nor t3, t2, zero
257 and t2, t1, t2 # t2 - current thread mode 267 and t2, t1, t2 /* t2 - current thread mode */
258 li v0, CKSEG1ADDR(RESET_DATA_PHYS) 268 li v0, CKSEG1ADDR(RESET_DATA_PHYS)
259 lw v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode 269 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
260 sll v1, 1 270 sll v1, 1
261 beq v1, t2, 1f # same as request value 271 beq v1, t2, 1f /* same as request value */
262 nop # nothing to do */ 272 nop /* nothing to do */
263 273
264 and t2, t1, t3 # mask out old thread mode 274 and t2, t1, t3 /* mask out old thread mode */
265 or t1, t2, v1 # put in new value 275 or t1, t2, v1 /* put in new value */
266 mtcr t1, t0 # update core control 276 mtcr t1, t0 /* update core control */
267 277
2681: wait 2781: wait
269 j 1b 279 j 1b