MIPS: Netlogic: USB support for XLP

The XLP USB controller appears as a device on the internal SoC PCIe
bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to:

* Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h
  to initialize the USB controller and define PCI fixups. The PCI
  fixups are to setup interrupts and DMA mask.
* Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt
  mapping for EHCI/OHCI interrupts.

Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3756/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 150 insertions, 1 deletions

diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index b93ed83474ec..5bd24b6a8f0b 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,2 +1,3 @@
 obj-y                           += setup.o platform.o nlm_hal.o
 obj-$(CONFIG_SMP)               += wakeup.o
+obj-$(CONFIG_USB)               += usb-init.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 3a4a17219723..fad2cae293c6 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -77,6 +77,18 @@ int nlm_irq_to_irt(int irq)
                return PIC_IRT_PCIE_LINK_2_INDEX;
         case PIC_PCIE_LINK_3_IRQ:
                return PIC_IRT_PCIE_LINK_3_INDEX;
+        case PIC_EHCI_0_IRQ:
+               return PIC_IRT_EHCI_0_INDEX;
+        case PIC_EHCI_1_IRQ:
+               return PIC_IRT_EHCI_1_INDEX;
+        case PIC_OHCI_0_IRQ:
+               return PIC_IRT_OHCI_0_INDEX;
+        case PIC_OHCI_1_IRQ:
+               return PIC_IRT_OHCI_1_INDEX;
+        case PIC_OHCI_2_IRQ:
+               return PIC_IRT_OHCI_2_INDEX;
+        case PIC_OHCI_3_IRQ:
+               return PIC_IRT_OHCI_3_INDEX;
         default:
                 return -1;
         }
@@ -97,6 +109,18 @@ int nlm_irt_to_irq(int irt)
                return PIC_PCIE_LINK_2_IRQ;
         case PIC_IRT_PCIE_LINK_3_INDEX:
                return PIC_PCIE_LINK_3_IRQ;
+        case PIC_IRT_EHCI_0_INDEX:
+                return PIC_EHCI_0_IRQ;
+        case PIC_IRT_EHCI_1_INDEX:
+                return PIC_EHCI_1_IRQ;
+        case PIC_IRT_OHCI_0_INDEX:
+                return PIC_OHCI_0_IRQ;
+        case PIC_IRT_OHCI_1_INDEX:
+                return PIC_OHCI_1_IRQ;
+        case PIC_IRT_OHCI_2_INDEX:
+                return PIC_OHCI_2_IRQ;
+        case PIC_IRT_OHCI_3_INDEX:
+                return PIC_OHCI_3_IRQ;
         default:
                 return -1;
         }
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
index 1f5e4cba891d..2c510d585447 100644
--- a/arch/mips/netlogic/xlp/platform.c
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -53,7 +53,7 @@
 
 static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
 {
-         return nlm_read_reg(p->iobase, offset);
+        return nlm_read_reg(p->iobase, offset);
 }
 
 static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c
new file mode 100644
index 000000000000..dbe083a93538
--- /dev/null
+++ b/arch/mips/netlogic/xlp/usb-init.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/usb.h>
+
+static void nlm_usb_intr_en(int node, int port)
+{
+        uint32_t val;
+        uint64_t port_addr;
+
+        port_addr = nlm_get_usb_regbase(node, port);
+        val = nlm_read_usb_reg(port_addr, USB_INT_EN);
+        val = USB_CTRL_INTERRUPT_EN  | USB_OHCI_INTERRUPT_EN |
+                USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN  |
+                USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
+        nlm_write_usb_reg(port_addr, USB_INT_EN, val);
+}
+
+static void nlm_usb_hw_reset(int node, int port)
+{
+        uint64_t port_addr;
+        uint32_t val;
+
+        /* reset USB phy */
+        port_addr = nlm_get_usb_regbase(node, port);
+        val = nlm_read_usb_reg(port_addr, USB_PHY_0);
+        val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
+        nlm_write_usb_reg(port_addr, USB_PHY_0, val);
+
+        mdelay(100);
+        val = nlm_read_usb_reg(port_addr, USB_CTL_0);
+        val &= ~(USB_CONTROLLER_RESET);
+        val |= 0x4;
+        nlm_write_usb_reg(port_addr, USB_CTL_0, val);
+}
+
+static int __init nlm_platform_usb_init(void)
+{
+        pr_info("Initializing USB Interface\n");
+        nlm_usb_hw_reset(0, 0);
+        nlm_usb_hw_reset(0, 3);
+
+        /* Enable PHY interrupts */
+        nlm_usb_intr_en(0, 0);
+        nlm_usb_intr_en(0, 3);
+
+        return 0;
+}
+
+arch_initcall(nlm_platform_usb_init);
+
+static u64 xlp_usb_dmamask = ~(u32)0;
+
+/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
+static void nlm_usb_fixup_final(struct pci_dev *dev)
+{
+        dev->dev.dma_mask               = &xlp_usb_dmamask;
+        dev->dev.coherent_dma_mask      = DMA_BIT_MASK(64);
+        switch (dev->devfn) {
+        case 0x10:
+               dev->irq = PIC_EHCI_0_IRQ;
+               break;
+        case 0x11:
+               dev->irq = PIC_OHCI_0_IRQ;
+               break;
+        case 0x12:
+               dev->irq = PIC_OHCI_1_IRQ;
+               break;
+        case 0x13:
+               dev->irq = PIC_EHCI_1_IRQ;
+               break;
+        case 0x14:
+               dev->irq = PIC_OHCI_2_IRQ;
+               break;
+        case 0x15:
+               dev->irq = PIC_OHCI_3_IRQ;
+               break;
+        }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
+                nlm_usb_fixup_final);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
+                nlm_usb_fixup_final);