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authorJayachandran C <jchandra@broadcom.com>2013-06-10 02:41:09 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-06-13 11:46:43 -0400
commit6099115e7e5e2c49d3822e093ca7df7015ca57a9 (patch)
treee5dbf33baf3549f2830fca700fb66fc42804f3f8 /arch/mips/netlogic
parent722138340b9f08d081255ba50928831a972c2e6f (diff)
MIPS: Netlogic: Remove workarounds for early SoCs
The XLPs in production do not need these workarounds. Remove the code and the associated ifdef. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r--arch/mips/netlogic/common/reset.S23
1 files changed, 1 insertions, 22 deletions
diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index 0ebd50a1d618..adb18288a6c0 100644
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -54,8 +54,6 @@
54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 54 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
55 SYS_CPU_NONCOHERENT_MODE * 4 55 SYS_CPU_NONCOHERENT_MODE * 4
56 56
57#define XLP_AX_WORKAROUND /* enable Ax silicon workarounds */
58
59/* Enable XLP features and workarounds in the LSU */ 57/* Enable XLP features and workarounds in the LSU */
60.macro xlp_config_lsu 58.macro xlp_config_lsu
61 li t0, LSU_DEFEATURE 59 li t0, LSU_DEFEATURE
@@ -63,10 +61,6 @@
63 61
64 lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */ 62 lui t2, 0xc080 /* SUE, Enable Unaligned Access, L2HPE */
65 or t1, t1, t2 63 or t1, t1, t2
66#ifdef XLP_AX_WORKAROUND
67 li t2, ~0xe /* S1RCM */
68 and t1, t1, t2
69#endif
70 mtcr t1, t0 64 mtcr t1, t0
71 65
72 li t0, ICU_DEFEATURE 66 li t0, ICU_DEFEATURE
@@ -74,12 +68,9 @@
74 ori t1, 0x1000 /* Enable Icache partitioning */ 68 ori t1, 0x1000 /* Enable Icache partitioning */
75 mtcr t1, t0 69 mtcr t1, t0
76 70
77
78#ifdef XLP_AX_WORKAROUND
79 li t0, SCHED_DEFEATURE 71 li t0, SCHED_DEFEATURE
80 lui t1, 0x0100 /* Disable BRU accepting ALU ops */ 72 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
81 mtcr t1, t0 73 mtcr t1, t0
82#endif
83.endm 74.endm
84 75
85/* 76/*
@@ -195,19 +186,7 @@ EXPORT(nlm_boot_siblings)
195 mfc0 v0, CP0_EBASE, 1 186 mfc0 v0, CP0_EBASE, 1
196 andi v0, 0x3ff /* v0 <- node/core */ 187 andi v0, 0x3ff /* v0 <- node/core */
197 188
198 /* Init MMU in the first thread after changing THREAD_MODE 189 beqz v0, 4f /* boot cpu (cpuid == 0)? */
199 * register (Ax Errata?)
200 */
201 andi v1, v0, 0x3 /* v1 <- thread id */
202 bnez v1, 2f
203 nop
204
205 li t0, MMU_SETUP
206 li t1, 0
207 mtcr t1, t0
208 _ehb
209
2102: beqz v0, 4f /* boot cpu (cpuid == 0)? */
211 nop 190 nop
212 191
213 /* setup status reg */ 192 /* setup status reg */