diff options
author | Jayachandran C <jchandra@broadcom.com> | 2013-08-11 05:13:53 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-03 17:22:18 -0400 |
commit | 13314a91f0588546023570cfc9a1cf4ca5027c75 (patch) | |
tree | 0285c565d3a8be3c32fa24a06066bfcebe503780 /arch/mips/netlogic | |
parent | 4f848ba5a041a4c52a501a0ffdd7ec62fae69762 (diff) |
MIPS: Netlogic: Fix DT flash size parameter
The flash chipselects can span 32MB, fix this in the built-in device
tree.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5704/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/netlogic')
-rw-r--r-- | arch/mips/netlogic/dts/xlp_evp.dts | 2 | ||||
-rw-r--r-- | arch/mips/netlogic/dts/xlp_svp.dts | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts index 7862a6f0a37e..89ad04808c02 100644 --- a/arch/mips/netlogic/dts/xlp_evp.dts +++ b/arch/mips/netlogic/dts/xlp_evp.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | #size-cells = <1>; | 14 | #size-cells = <1>; |
15 | compatible = "simple-bus"; | 15 | compatible = "simple-bus"; |
16 | ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG | 16 | ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG |
17 | 1 0 0 0x16000000 0x01000000>; // GBU chipselects | 17 | 1 0 0 0x16000000 0x02000000>; // GBU chipselects |
18 | 18 | ||
19 | serial0: serial@30000 { | 19 | serial0: serial@30000 { |
20 | device_type = "serial"; | 20 | device_type = "serial"; |
diff --git a/arch/mips/netlogic/dts/xlp_svp.dts b/arch/mips/netlogic/dts/xlp_svp.dts index 5aba17e7f200..1ebd00edaacc 100644 --- a/arch/mips/netlogic/dts/xlp_svp.dts +++ b/arch/mips/netlogic/dts/xlp_svp.dts | |||
@@ -14,7 +14,7 @@ | |||
14 | #size-cells = <1>; | 14 | #size-cells = <1>; |
15 | compatible = "simple-bus"; | 15 | compatible = "simple-bus"; |
16 | ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG | 16 | ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG |
17 | 1 0 0 0x16000000 0x01000000>; // GBU chipselects | 17 | 1 0 0 0x16000000 0x02000000>; // GBU chipselects |
18 | 18 | ||
19 | serial0: serial@30000 { | 19 | serial0: serial@30000 { |
20 | device_type = "serial"; | 20 | device_type = "serial"; |